Improvement of neural network classifier using floating centroids

This paper presents a novel technique—Floating Centroids Method (FCM) designed to improve the performance of a conventional neural network classifier. Partition space is a space that is used to categorize data sample after sample is mapped by neural network. In the partition space, the centroid is a point, which denotes the center of a class. In a conventional neural network classifier, position of centroids and the relationship between centroids and classes are set manually. In addition, number of centroids is fixed with reference to the number of classes. The proposed approach introduces many floating centroids, which are spread throughout the partition space and obtained by using K-Means algorithm. Moreover, different classes labels are attached to these centroids automatically. A sample is predicted as a certain class if the closest centroid of its corresponding mapped point is labeled by this class. Experimental results illustrate that the proposed method has favorable performance especially with respect to the training accuracy, generalization accuracy, and average F-measures.     

A CMOS neural network for pattern association

The authors present an analog complementary metal-oxide semiconductor (CMOS) version of a model for pattern association, along with discussions of design philosophy, electrical results, and a chip architecture for a 512-element, feed-forward IC. They discuss hardware implementations of neural networks and the effect of limited interconnections. They then examine network design, processor-element design, and system operation     

CMOS current-mode neural associative memory design with on-chiplearning

Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.     

A neural network model of memory under stress

A model that attempts to simulate animal memory under stress is presented. For this purpose a model of selectable multiple associative memories is given. We consider two underlying types of memories: stressed and unstressed, implemented on the same neural network. In our model, learning into one or the other type of memory is done according to the stress of the individual at the time of learning. Memory retrieval is obtained according to a continuous function of the stress of the individual at the time of retrieval, who for low stress retrieves unstressed associations and for high stress retrieves stressed associations. Several biological results supporting this model are presented. A mathematical proof on the behaviour of the basins of attraction of the network as a function of stress is presented. Also a generalization to selectable multiple coexisting memories is given, and engineering and other applications of the model are suggested.     

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

 Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against V _dd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.     

Sequence memory based on an oscillatory neural network

In the brain,the discrete elements in a temporal order is encoded as a sequence memory.At the neural level,the reproducible sequence order of neural activity is very crucial for many cases.In this paper,a mechanism for oscillation in the network has been proposed to realize the sequence memory.The mechanism for oscillation in the network that cooperates with hetero-association can help the network oscillate between the stored patterns,leading to the sequence memory.Due to the oscillatory mechanism,the firing history will not be sampled,the stability of the sequence is increased,and the evolvement of neurons’states only depends on the current states.The simulation results show that neural network can effectively achieve sequence memory with our proposed model.     

Survey of neural network technology for automatic targetrecognition

A review is presented of ATR (automatic target recognition), and some of the highlights of neural network technology developments that have the potential for making a significant impact on ATR are presented. In particular, neural network technology developments in the areas of collective computation, learning algorithms, expert systems, and neurocomputer hardware could provide crucial tools for developing improved algorithms and computational hardware for ATR. The discussion covers previous ATR system efforts. ATR issues and needs, early vision and collective computation, learning and adaptation for ATR, feature extraction, higher vision and expert systems, and neurocomputer hardware.     

基于量子门组的量子神经网络模型及其应用

为进一步提高量子神经网络的性能,结合目前神经网络机理的研究进展,提出了一种基于量子门组的量子神经元模型,建立了量子门组量子神经网络（Quantum Gate Set Neural Network,QGSNN）。该算法由输入层、隐含层和输出层组成,该算法将转换后的量子态训练样本作为输入。利用量子旋转门和通用量子门完成旋转、选择、翻转和聚合等一系列操作,并完成了网络参数的更新。将训练后的结果输出。QGSNN算法的泛化能力在数学上得到了证明,并利用两个仿真实验对该方法进行验证。实验结果表明,与普通神经网络和普通量子神经网络相比,QG-SNN算法在泛化性能、鲁棒性、准确率和执行时间等方面具有较好的效果。     

神经网络关联存储器的设计及应用

神经网络的存储能力一直是一个重大的缺陷,其存储主要体现在权重系数上,因此参数量一多,训练起来就十分困难。给神经网络设计一个外部关联存储器,能有效对神经网络的输入进行关联查询,并将查询的结果作为辅助输入传入到神经网络中去。此外,设计了自然语言语句的向量嵌入模型,并将模型和关联存储器集合起来形成一个自动关联语句语义向量的关联存储系统,其性能指标达到了设计要求。     

Sparsification from dilute connectivity in a neural network model of memory.

Several hypotheses concerning implementations of associative memory in the brain rely on analyses of the capabilities of simple network models. However, the low connectivity of cerebral networks imposes constraints which sometimes do not arise clearly from such analyses. We investigate an aspect of a simple, dilute network's operation that is sometimes overlooked, namely the setting of activation thresholds. An examination of several criteria for optimal threshold assignment affords several new insights. It becomes apparent that the network's capacity (which is simply derived) is insufficient to characterize the quality of its performance. We derive the degree of 'sparsification' or decrease in firing probability that arises from dilution, and also the consequent losses in representational ability, and propose that they should also be taken into account. To evaluate the model's performance and suitability, we argue that one should explicitly consider the trade-off that exists between storage of patterns and preservation of information, and its consequent constraints.     

小世界神经网络中的联想记忆研究

本文研究了基于小世界结构的神经网络中的联想记忆模型.网络恢复存储模式的行为其实是无序参数为一有限值时的相位变化.越是规则的网络越是难以恢复记忆模式,且容易变成混合状态.另外,在无序参数的值适中时,对于一定数量的存储模式,最终得到恢复的效果可以达到最大.     

Using distributed ledger technology to democratize neural network training

Artificial Intelligence has regained research interest, primarily because of big data. Internet expansion, social networks and online sensors led to the generation of an enormous amount of information daily. This unprecedented data availability boosted Machine Learning. A research area that has greatly benefited from this fact is Deep Neural Networks. Nowadays many use cases require huge models with millions of parameters and big data are proven to be essential to their proper training. The scientific community has proposed several methods to generate more accurate models. Usually, these methods need high performance infrastructure, which limits their applicability to large organizations and institutions that have the required funds. Another source of concern is privacy; anyone using the leased processing power of a remote data center, must trust another entity with their data. Unfortunately, in many cases sensitive data were leaked, either for financial exploitation or due to security issues. However, there is a lack of research studies when it comes to open communities of individuals with commodity hardware, who wish to join forces in a way that is non-binding and without the need for a central authority. Our work on LEARNAE attempts to fill this gap, by creating a way of providing training in Artificial Neural Networks, featuring decentralization, data ownership and fault tolerance. This article adds some important pieces to the puzzle: It studies the resilience of LEARNAE when dealing with network disruptions and proposes a novel way of embedding low-energy sensors that reside in the Internet of Things domain, retaining at the same time the established distributed philosophy.

     

基于神经网络的肉类新鲜度辨识技术

阐述了肉类新鲜度检测识别机理,构建了由气体传感器阵列、数据采集单元、神经网络组成的智能检测辨识系统。通过猪肉样本的测试与分析表明:该方法可实时准确地识别肉类新鲜度,辨识准确率可达90%以上。     

Innovation of enterprise technology alliance based on BP neural network

Neural Computing and Applications - Enterprise technology alliance innovation is the power force of enterprise development. At present, the enterprise science and technology alliance is affected by...     

内存数据库技术在电网实时监测中的应用研究

对现有的内存数据库体系结构进行了改进,引进了数据失步缓冲机制和自适应文件缓冲机制,并将改进后的内存数据库技术整合到企业电网实时监测系统的整体架构中,提出了一套完整的基于内存数据库技术的企业电网实时监测系统的架构模型,该模型在保证数据实时性的同时可提高监测系统的并行处理能力和稳定性.与内存数据库相关的数据接口访问、数据同步等关键技术也进行了详细的分析,最后给出了系统的实际应用案例.     

模糊神经网络技术在铅锌烧结过程中的应用研究

烧结过程是铅锌冶炼过程中的一个重要环节,但烧结过程的建模难度较大。文章提出了一种烧结块成分预测的模糊神经网络模型,并通过仿真验证了其可行性。     

Variability in nanoscale CMOS technology

Moore’s Law technology scaling has improved VLSI performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore’s Law, a variety of challenges will need to be overcome. One of these challenges is management of process variation. This paper discusses the importance of process variation in modern CMOS transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques (including circuit and SRAM data...     

基于自组织神经网络的多传感器遥感图像融合技术

多传感器遥感图像融合是一种遥感信息综合分析与处理的技术,其研究正成为遥感学科领域的热门课题之一。利用自组织特征映射神经网络具有较好的聚类特性,对多源遥感图像进行高水平的分类与融合。通过对GMS 5卫星图像融合前后性质的比较和融合质量的评估,不难发现:融合后的图像不论在视觉效果上还是在噪声特性上都有了很大的改善。     

BP网络与RBF网络在感官评估中应用比较

介绍BP网络与RBF网络的方法原理以及二者在感官评估中的应用.利用企业提供的单料烟感官数据设计建立BP网络和RBF网络模型,并利用模型预测单料烟感官质量指标,然后通过行业专家提供的符合度公式对建立的模型进行评估,评估结果以百分比的形式展示.实验结果表明:在感官评估应用中,RBF网络模型预测性能优于BP网络模型.     

A parallel genetic/neural network learning algorithm for MIMDshared memory machines

A new algorithm is presented for training of multilayer feedforward neural networks by integrating a genetic algorithm with an adaptive conjugate gradient neural network learning algorithm. The parallel hybrid learning algorithm has been implemented in C on an MIMD shared memory machine (Cray Y-MP8/864 supercomputer). It has been applied to two different domains, engineering design and image recognition. The performance of the algorithm has been evaluated by applying it to three examples. The superior convergence property of the parallel hybrid neural network learning algorithm presented in this paper is demonstrated.