Development of integrated cable/telephony in the United Kingdom

The United Kingdom offers franchised cable television operators the unique opportunity to provision a competitive telephony service in addition to multichannel television services. The TeleWest Communications Group Plc., a joint venture between Telecommunication Inc. (TCI) and US West, have taken advantage of this opportunity to invest, operate, and assist in the operation of CATV/telephony in the United Kingdom. TeleWest owns or invests in 24 franchises, totalling approximately 3.6 million homes passed. Twenty-one of the 24 franchises wholly owned or invested in by TeleWest are offering competitive telephony as of the end of 1994. Others are set to start in the 1995-96 time frame. The article discusses the development of network architectures in support of TeleWest's cable/telephony opportunities in the United Kingdom. The article begins with an account of the history of U.K. cable/telephony, continues with the early developments and drivers of the architecture, discusses the current architecture and build, and concludes with an overview of future development and directions for the architecture     

A wide band up-conversion mixer for cable television tuner

An up-conversion mixer implemented in a 0.35μm SiGe BiCMOS technology for a double conversion cable TV tuner is described, The mixer converts the 100MHz to 1000MHz band to the Intermediate Frequency of 1GHz above. The mixer meets the linearity and noise figure requirements for a TV tuner. The noise figure （IF） of 19.2-17.5dB, ldB compression of 12.1dBm, and gain of-1-0.7dB in the 900MHz band are achieved at a supply voltage of 5V. The power consumption is 47mW.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

A low-power NMOS transmit/receive IC filter for PCM telephony

A very low-power single chip NMOS implementation of the transmit and receive PCM filters used in telephony applications is described. The circuit utilizes doubly-terminated switched capacitor low-pass and high-pass filters and meets accepted requirements without trimming. The filters have low idle-channel noise, consume only 20 mW of power, and are realized in a small area of silicon. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described.     

一种基于锗硅双极CMOS工艺的多频段移动电视调谐器芯片

本文给出了一种应用于多频段移动电视调谐器的射频芯片的设计和测试结果。射频调协器由宽带射频前端电路,模拟基带电路,全集成的小数频率综合器和I2C数字接口电路组成。为了满足移动电视标准苛刻的临道抑制指标,同时兼顾低功耗、低成本的要求,本设计采用了带局部自动增益控制的直接下变频接收机方案。为进一步提高临道抑制的性能,基带频道选择滤波器采用了8阶椭圆有源RC的结构,具有阻带衰减高和过渡带极陡的特点。射频调协器芯片采用0.35 μm锗硅双极CMOS工艺制成,硅片面积为5.5 mm2。芯片采用3.0V单电源供电,消耗50mA电流。在CMMB应用中,系统灵敏度达到-97 dBm,临道抑制优于40 dB。     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A low-power integrated circuit for remote speech recognition

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 μW at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-μm, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 μJ. It achieves recognition rates over 98% in isolated-word speech recognition tasks     

Microcomputer applications in telephony

The application of microcomputers and other large-scale integrated (LSI) circuit products such as microcomputer memory peripherals, digital coders and decoders (codec), and channd filters to telephone switching systems, transmission systems, and to high-feature telephone instruments is discussed. Switching and transmission systems which use standardized digital transmission formats are described, and line circuit and common control functions are briefly discussed for digital switching system architectures using microcomputer control. A high-feature electronic telephone and trends in digital telephony are also reviewed as they relate to potential applications of products based on large scale integration techniques.     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

Monolithically integrated low-power phototransceivers foroptoelectronic parallel sensing and processing applications

A low-power GaAs-based monolithically integrated phototransceiver, consisting of a high-gain heterojunction phototransistor (WPT) and a microcavity light-emitting diode (MCLED) or a low-threshold vertical-cavity surface-emitting laser (VCSEL), is demonstrated. The HPT and MCLED/VCSEL are grown by molecular-beam epitaxy in a single step. The phototransistor exhibits a responsivity of 60 A/W at an input power of 1 μW. The input and output wavelengths are 850 and 980 nm, respectively. The MCLED-based phototransceiver exhibits an optical gain of 7 dB and power dissipation of 400 μW for an input power of 1.5 μW. The small signal modulation bandwidth is 80 MHz. On the other hand, the VCSEL-based phototransceiver exhibits an optical gain of 10 dB and power dissipation of 760 μW for an input power of 2.5 μW     

A multi-purpose CMOS sensor interface for low-power applications

A dedicated low-power CMOS transponder microchip is presented as part of a novel telemetry implant for biomedical applications. This mixed analog-digital circuit contains an identification code and collects information on physiological parameters, i.e., body temperature and physical activity, and on the status of the battery. To minimize the amount of data to be transmitted, a dedicated signal processing algorithm is embedded within its circuitry. All telemetry functions (encoding, modulation, generation of the carrier) are implemented on the integrated circuit. Emphasis is on a high degree of flexibility towards sensor inputs and internal data management, extreme miniaturization, and low-power consumption to allow a long implantation lifetime     

A single-chip NMOS dual channel filter for PCM telephony applications

The implementation of a completely monolithic channel filter containing all frequency selective functions associated with a PCM line interface is described. The circuit utilizes switched capacitor techniques. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described. Experimental results are presented.     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

A low-power dual-mode video decoder for mobile applications

The objective of this article is to highlight design challenges for low-power and dual-video standard requirements, especially in mobile applications. Due to the advent of the newly announced H.264, a generic problem of standard incompatibility has appeared between H.264 and prevalent MPEG-x video standards, which must be resolved on both algorithmic and architectural levels. Furthermore, several low-power techniques targeted at achieving lower memory requirements and processing cycles are also described and discussed.     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

A low-power backward equalizer for DFE read-channel applications

A general-purpose backward equalizer for use in decision feedback equalization systems is described. Current-steering techniques are used to achieve high-speed low-power operation. A four-tap prototype for use in a magnetic disk read-channel chip has been implemented in a standard digital 1.2-μm n-well CMOS process. The circuit operates at 67 MHz and dissipates 1 mW/tap from a 3.3 V power supply     

Passive optical networks for local telephony and cable TV provision

Recent proposals have been made for a passive optical local access network (PON) for telephony and cable TV applications. These are leading to the design of new telecommunications customer access equipment whose functional requirements are discussed, together with details of the system demonstrators at BTRL. Possible sccenarios for network deployment are presented.     

A low-power low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.     

Modeling call control for distributed applications in telephony

The advanced intelligent network (AIN) architecture, an environment in which distribution applications are designed, developed, and deployed independent of the network implementation by different service developers, on possibly different platforms, at different times, is considered. The focus is primarily on support for call-processing applications through call-modeling techniques. However, the entities of NECs application service processor (ASP) architecture as a whole are briefly described to provide a basic understanding of the scope of the call model. The call-modeling concepts discussed at the Bellcore-sponsored Multi-Vendor Interaction forum are compared with NEC's call-modeling concepts. A simple approach (i.e. the logical path) for controlling the execution of FCs (function components) when multiple AIN services are active on a call is suggested. An object-oriented implementation based on the NEC call model is described     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.