A test structure advisor and a coupled, library-based teststructure layout and testing environment

A new test chip design environment, based on commercial tools, containing a test structure advisor and a coupled, library-based layout and testing environment has been developed that dramatically increases productivity. The test structure advisor analyzes cross sections of devices to recommend a comprehensive list of diagnostic and parametric test structures. These test structures can then be retrieved from the libraries of parameterized structures, customized, and placed in a design to rapidly generate customized test chips. Coupling of the layout and test environments enables the automatic generation of the vast majority of the parametric test software. This environment, which has been used to design test chips for a low-power/low-voltage CMOS process, a BiCMOS trench process, and a TFT process, results in an estimated tenfold increase in productivity. In addition, the redesign of five modules of Stanford's existing BiCMOS test chip, using parameterized test structures, showed an 8× improvement in layout time alone     

高性能模拟集成电路工艺技术

介绍了模拟集成电路工艺的发展过程和现状，讨论了国内的BiCMOS工艺、互补双极工艺(CB)、和SOI双极工艺的最新进展。重点介绍了BiCMOS工艺的研完与开发，指出了模拟集成电路工艺的发展趋势。     

亚微米BiCMOS电路纵向NPN管的ESD保护研究

文章以0.6μmN外延BiCMOS工艺为基础,研究了纵向NPN管的ESD保护行为,并对不同版图结构的纵向NPN管进行了ESD行为研究。实验表明,由于基区的内在电阻不一样,在该工艺条件下,CEB、CEBE结构比CBE、CBEB结构SNAPBACK效应明显,机器模式下ESD保护能力强。此外,还研究了兼容低压Vz工艺,单级保护NMOS输出管的纵向NPN器件的ESD行为,流片显示采用EB结齐纳击穿的纵向NPN能有效单级保护CMOS的输出级。     

Novel merged BiCMOS circuit structures

Novel merged BiCMOS circuit structures are presented. They offer an area saving of 20-30% compared with conventional BiCMOS structures. The DC and the transient performance of the merged structures are verified using the two-dimensional PISCES-IIB device simulator.<>     

High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Lateral p-n-p bipolar junction transistors (BJTs) fabricated using a bulk 0.25 μm CMOS technology are presented. The devices are structurally the same as p-MOSFETs in which the gate and the n-well are internally connected to form the base. The p-n-p BJT has an adjustable current gain which can be higher than 1000 and its peak cutoff frequency is 3.7 GHz. Since the lateral p-n-p BJT is fully process compatible with submicrometer CMOS and/or BiCMOS technologies, extension to a BiCMOS and/or complementary BiCMOS process is readily achieved     

A BiCMOS continuous-time filter for video signal processingapplications

A fully integrated BiCMOS continuous-time filter for video signal processing applications is presented. It incorporates an input clamping circuit, a third-order equalizer, a fifth-order elliptic filter with sinx/x correction, and a 75-Ω driver. The architectures of the input and output amplifiers as well as the filter and the equalizer are chosen based on the extensive study of circuit structures and Monte Carlo simulation to meet the linearity requirement for the broadcast-quality video system. The complete chip achieves a low-pass filter response with a 5.5-MHz cutoff frequency (f_cc), 0.3-dB passband ripple, 20-ns group delay variation up to 0.9 f_c, and 43-dB attenuation at 1.45 f_c. With a nominal 2-Vpp signal at the output, measured results show 0.2% differential gain, 0.38° differential phase, and 1.7-mV rms noise demonstrating 10-bit linearity in a 1.5-μm 4-GHz BiCMOS process technology. The filter active area is 8 mm² and it dissipates 350 mW in a single 5-V power supply     

A 300-MHz BiCMOS serial data transceiver

A BiCMOS circuit for serial data communication is presented. The chip has phase-locked loops for transmit frequency synthesis and receive clock recovery, serial-to-parallel and parallel-to-serial converters, and encode and decode functions. Since this is a mixed-analog/digital design, and the transmitter and receiver operate asynchronously, many techniques are used to decrease noise coupling. A 1.2 μm BiCMOS process allows operation at speeds of 300 MHz along with this high level of system integration, and the chip consumes less than 1 W from a single 5 V supply     

A direct digital frequency synthesizer with high-speed current-steering DAC

A high-speed SiGe BiCMOS direct digital frequency synthesizer (DDS) is presented. The design in tegrates a high-speed digital DDS core, a high-speed differential current-steering mode 10-bit D/A converter, a serial/parallel interface, and clock control logic. The DDS design is processed in 0.35 μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency. The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400+ MHz.     

Low-power BiCMOS circuits for high-speed interchip communication

A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-μm BiCMOS technology are also presented     

BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications     

Automatic generation of thin film process flows. II. Recipegeneration, flow evaluation, and system framework

This paper is the second in a series of two papers describing the methodology and algorithms used in the development of MISTIC (Michigan synthesis tools for integrated circuits). Part I [see ibid., vol. 12, no. 1, Feb. 1999] discussed the basic topological algorithms used to produce generic sequences of processing steps required for the fabrication of a given device structure. Part II discusses the expansion of these sequences into complete process flows. This procedure involves the selection of specific recipes from a set of available processing resources and the calculation of recipe parameters. These processing resources are stored in a database central to the MISTIC system framework. Since many process flows are generated for a given device, the paper also discusses the calculation of suitable figures of merit. The capabilities of the MISTIC system are demonstrated with a BiCMOS example. The MISTIC system framework which contains the basic compiler and several supporting modules: a device builder, process viewer, and database editor is also presented     

Fault characterization, testing considerations, and design fortestability of BiCMOS logic circuits

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented     

Scaling of digital BiCMOS circuits

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling     

A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

An ultra-low-power, 2$ ^7-$1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz$f_T$SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.     

BiCMOS circuits for DPCM coders in HDTV systems

Three different strategies used to enhance the speed performance of differential pulse-code-modulation (DPCM) coders are reviewed. The first strategy is the reduction of the number of components located in the time-critical recursive loop. The second is the use of a BiCMOS technology, and the third is the development of high-speed circuit techniques. Prototype chips prove that a 2.5-μm process is feasible for implementation of DPCM coders operating at 54 MHz. Another test structure shows a BiCMOS sequencer with 64 product terms running at 80 MHz with 125-mW power consumption     

新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

BiCMOS结构中阱特性的研究

叙述了以双极型工艺为主体的ＢｉＣＭＯＳ结构中ｐ阱电阻比值非线性的特性及其与芯片合格率的关系。在ｐ阱下面采用埋层，抑制或消除了ＢｉＣＯＭＳ中；ｐ阱结构的寄生效应，从而提高了芯片合格率。     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

A polysilicon contacted subcollector BJT for a three-dimensionalBiCMOS process

A polysilicon contacted subcollector (PCS) bipolar junction transistor (BJT) was fabricated using selective epitaxial growth (SEG) of silicon to form the active region. The fabrication is the first step in the development of a novel 3-D BiCMOS process. To study the efficacy of the polysilicon collector contact, three types of BJTs were fabricated and their collector resistances were compared. These were the PCS BJT, a BJT fabricated in SEG silicon grown from a shallow trench incorporating a shallow collector contact with a buried layer, and a BJT fabricated in the silicon substrate with a shallow collector contact but no buried layer. The PCS BJT exhibited the smallest collector resistance as well as excellent device characteristics, demonstrating its viability for a 3-D BiCMOS process     

An 8-b, 40 msamples/s switched-current-mode track-and-hold circuiton a BiCMOS sea-of-gates array

A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm²