A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO₂ n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO₂ by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO₂ resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks.     

Degradation of TiAlNiAu as ohmic contact metal for GaN HEMTs

Ti/Al/Ni/Au stack is widely used to form ohmic contact on GaN based semiconductor material. Long term thermal storage tests conducted to assess AlGaN/GaN HEMT technology have shown a dramatic degradation of this metal when stored more than 100 h at temperatures above 340 °C. The first evidence of degradation is the increase of resistance and the surface morphology evolution leading passivation film to crack. AES and EDS analyses have demonstrated that Ga out-diffusion and Au inter-diffusion are the root causes of this degradation. Cross sections outlined voids occurrence.     

Characterization of nickel Germanide thin films for use as contacts to p-channel Germanium MOSFETs

We have measured the physical properties and resistivity of nickel germanide thin films formed by the rapid thermal annealing of nickel metal on p-type germanium substrates. Rutherford back scattering and high-resolution electron diffraction confirm that the stoichiometry of the resulting nickel germanide film corresponds to NiGe and has an orthorhombic unit cell with dimensions comparable to that of bulk samples. Transmission electron microscopy shows a poly-crystalline film structure with grain size > 0.1 /spl mu/m. The resistivity values for films annealed in the range 350/spl deg/C-500/spl deg/C are comparable to those of metal silicides. Measurements of the specific contact resistance suggest that values approaching 2 /spl times/ 10/sup -7/ /spl Omega/.cm/sup 2/ can be realized using NiGe formed on heavily doped p-type germanium.     

Nickel-based contact metallization for SiGe MOSFETs: progress and challenges

The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni–Si_1−xGe_x interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi_1−uGe_u (i.e. mono-germanosilicide, with u possibly different from x in the Si_1−xGe_x) is the most desirable phase due to its low specific resistivity of 12–25 μΩcm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi_1−uGe_u on single-crystal and polycrystalline Si_1−xGe_x substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d’Heurle [J. Mater. Res. 3 (1988) 167] and by d’Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi_1−uGe_u are also covered. The electrical properties of the NiSi_1−uGe_u–Si_1−xGe_x contact are discussed referring to our latest experimental results.     

Effects of localized contamination with copper in MOSFETs

Using a relatively large size MOSFET (W/L= 15/15 /spl mu/m), we investigated the degradation of MOSFET characteristics due to localized copper contamination. In order to contaminate a part of the active region of MOSFET, silicon nitride (Si/sub 3/N/sub 4/) over the active region, which is known to be a protective film against copper, was etched by reactive ion etching (RIE). As the area of localized copper contamination is about 3-4 /spl mu/m or above, apart from the edge of the gate electrode, no degradation was observed after thermal treatment at 450/spl deg/C for 2 h in N/sub 2/ ambient, based on the result of the increase in interface trap density (/spl Delta/D/sub it/).     

Fabrication and characterization of sub-quarter-micron MOSFETs witha copper gate electrode

Sub-0.25-μm P- and N-MOSFETs with a chemical vapor deposited copper gate electrode were fabricated using a novel nitride cast method wherein a silicon nitride gate is used as a stand-in gate which is then replaced by Cu with a PVD TiN barrier metal after source/drain formation. The maximum processing temperature after copper deposition is 400°C. Excellent device performance was obtained on both P- and N-MOSFET. No signs of copper diffusion were observed after device fabrication and after bias-temperature stress tests at 200°C     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Simulation study on comparison between metal gate and polysilicongate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage     

Anodic oxide film as gate insulator for InP MOSFETs

An anodic oxide film of InP, which had an interface state density of ? 1011 cm?2 eV?1 near midgap and worked well as the gate insulator for InP MOSFETs, was obtained by optimising its preparation conditions. The excellence of the anodic oxide as a gate insulator was confirmed by a high electron effective mobility (1500 cm2/Vs) in the accumulation-mode InP MOSFETs.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

Impact of dummy metal filling strategy dedicated to inductors integrated in advanced thick copper RF BEOL

A complete strategy to manage dummy fills inside a large spectrum of integrated RF inductors realized in an advanced thick copper RF back end of line (BEOL) is presented here. The main motivation of this paper is first to evaluate through a design of experiment (DOE) modeling, the impact on RF inductor performances of dummy metal fills inserted inside the coils, and then determine the right metal fill density to insert in order to be compliant with Digital metal density rules without degrading their electrical performances.     

Characterization issues of gate geometry in multifinger structurefor RF-SOI MOSFETs

In this letter, we propose that f_T and f_max properties in partially depleted SOI devices were analyzed in terms of gate electrode layout, body instability, and body resistance of multifinger structure. The speed characteristics were a strong function of the number of fingers and gate types such as T-gate and H-gate structures and were evaluated by g_m variation (Δg_m ), extra parasitic capacitance (ΔC_gs), and ac body instability     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.     

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler-Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Influence of surface contamination on metal/metal bond contact quality

The influence of surface cleanliness of Au/Ni coated multichip materials (MCMs), Ag plated Cu lead frames, and Al bond pads on semiconductor chips on the strength of Au wire bond contacts has been investigated. A clean surface is important for good adhesion in any kind of attachment process. Investigations by means of x-ray photoelectron spectroscopy have been performed on the bond substrates to determine the chemical composition, the nature as well as the thickness of the contamination layer. The influence of contamination on bond contact quality has been examined by pull force measurements, which is an established test method in semiconductor packaging industry for evaluating the quality of wire bonds. The results clearly show that a strong correlation between the degree of contamination of the substrate and pull strength values exists. Furthermore, a contamination thickness limiting value of 4 nm for Au and Ag substrates was determined, indicating good wire bond contact quality. The effect of plasma cleaning on wire bondability of metallic and organic (MCMs) substrates has been examined by pull force measurements. These results confirm the correlation between surface contamination and the strength of wire bond contacts for Au/Ni coated MCMs and Ag plated Cu lead frames. Atomic force microscopy measurements have been performed to determine the roughness of bond surfaces, demonstrating the importance of nanoscale characterization with regard to the bonding behavior of the substrates. Finally, bonding substrates used in integrated circuit packaging are discussed with regard to their Au wire bonding behavior. The Au wire bonding process first results in a cleaning effect of the substrate to be joined and secondly enables the change of bonding energy into frictional heat giving rise to an enhanced interdiffusion at the interface.     

Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs

The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000 °C annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect.     

New copper seed-layer enhancement process metrology for advanced dual-damascene interconnects

The extendibility of the physical vapor deposition (PVD), seed-layer deposition process for future devices needs to be enhanced with electrochemical techniques. Developing analytical techniques for the plating bath is a particular challenge because bath ingredients are often proprietary and difficult to ascertain. The feasibility of using an ion chromatography for an electrochemical copper, seed-layer enhancement (SLE) process metrology is studied. It is shown that the ion-chromatography method can be used to precisely determine the composition dynamics in a copper SLE plating bath. The bath concentration dynamics are found to be significant in influencing the electroplated Cu film properties, i.e., the resistivity and surface roughness. An excellent correlation exists between the ion chromatograms and the electroplated Cu film properties, suggesting that the ion-chromatography method is a powerful method.     

Characterization of probe contact noise for probes used inwafer-level testing

The characteristics of probe contact noise for tungsten probes used in wafer-level testing are presented. The effects of the biasing current and the probe contact resistance, R_c, on the probe contact noise were investigated. This information is required for low-noise probe design as well as for reduction of the contact noise effects on sample noise measurements. The results show that the spectral density of the probe contact noise voltage has a 1/f frequency dependence and is proportional to V_c²R_c^Γ where Γ is a constant which has a value between -0.1 and 0.6 depending on the conditions of the contact interfaces