A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO₂ n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO₂ by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO₂ resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks.     

Degradation of TiAlNiAu as ohmic contact metal for GaN HEMTs

Ti/Al/Ni/Au stack is widely used to form ohmic contact on GaN based semiconductor material. Long term thermal storage tests conducted to assess AlGaN/GaN HEMT technology have shown a dramatic degradation of this metal when stored more than 100 h at temperatures above 340 °C. The first evidence of degradation is the increase of resistance and the surface morphology evolution leading passivation film to crack. AES and EDS analyses have demonstrated that Ga out-diffusion and Au inter-diffusion are the root causes of this degradation. Cross sections outlined voids occurrence.     

Characterization of nickel Germanide thin films for use as contacts to p-channel Germanium MOSFETs

We have measured the physical properties and resistivity of nickel germanide thin films formed by the rapid thermal annealing of nickel metal on p-type germanium substrates. Rutherford back scattering and high-resolution electron diffraction confirm that the stoichiometry of the resulting nickel germanide film corresponds to NiGe and has an orthorhombic unit cell with dimensions comparable to that of bulk samples. Transmission electron microscopy shows a poly-crystalline film structure with grain size > 0.1 /spl mu/m. The resistivity values for films annealed in the range 350/spl deg/C-500/spl deg/C are comparable to those of metal silicides. Measurements of the specific contact resistance suggest that values approaching 2 /spl times/ 10/sup -7/ /spl Omega/.cm/sup 2/ can be realized using NiGe formed on heavily doped p-type germanium.     

Nickel-based contact metallization for SiGe MOSFETs: progress and challenges

The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni–Si_1−xGe_x interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi_1−uGe_u (i.e. mono-germanosilicide, with u possibly different from x in the Si_1−xGe_x) is the most desirable phase due to its low specific resistivity of 12–25 μΩcm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi_1−uGe_u on single-crystal and polycrystalline Si_1−xGe_x substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d’Heurle [J. Mater. Res. 3 (1988) 167] and by d’Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi_1−uGe_u are also covered. The electrical properties of the NiSi_1−uGe_u–Si_1−xGe_x contact are discussed referring to our latest experimental results.     

Effects of localized contamination with copper in MOSFETs

Using a relatively large size MOSFET (W/L= 15/15 /spl mu/m), we investigated the degradation of MOSFET characteristics due to localized copper contamination. In order to contaminate a part of the active region of MOSFET, silicon nitride (Si/sub 3/N/sub 4/) over the active region, which is known to be a protective film against copper, was etched by reactive ion etching (RIE). As the area of localized copper contamination is about 3-4 /spl mu/m or above, apart from the edge of the gate electrode, no degradation was observed after thermal treatment at 450/spl deg/C for 2 h in N/sub 2/ ambient, based on the result of the increase in interface trap density (/spl Delta/D/sub it/).     

0.13μm射频MOS场效应晶体管特性及模拟

采用0.13μm CMOS射频和混合信号工艺进行了射频nMOS场效应晶体管版图的优化设计和芯片制作.对制作的射频nMOS器件进行了直流特性和S参数测试,测试结果表明射频nMOS管的特征频率fT达到了93GHz,fmax超过了90GHz.采用小信号等效电路模型对该nMOS管的交流特性进行了模拟.在100MHz到30GHz频率范围内得到了与测试结果相吻合的仿真结果.     

0.13μm射频MOS场效应晶体管特性及模拟

采用0.13μm CMOS射频和混合信号工艺进行了射频nMOS场效应晶体管版图的优化设计和芯片制作. 对制作的射频nMOS器件进行了直流特性和S参数测试，测试结果表明射频nMOS管的特征频率f_T达到了93GHz, f_max超过了90GHz. 采用小信号等效电路模型对该nMOS管的交流特性进行了模拟. 在100MHz到30GHz频率范围内得到了与测试结果相吻合的仿真结果.     

Fabrication and characterization of sub-quarter-micron MOSFETs witha copper gate electrode

Sub-0.25-μm P- and N-MOSFETs with a chemical vapor deposited copper gate electrode were fabricated using a novel nitride cast method wherein a silicon nitride gate is used as a stand-in gate which is then replaced by Cu with a PVD TiN barrier metal after source/drain formation. The maximum processing temperature after copper deposition is 400°C. Excellent device performance was obtained on both P- and N-MOSFET. No signs of copper diffusion were observed after device fabrication and after bias-temperature stress tests at 200°C     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Simulation study on comparison between metal gate and polysilicongate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage     

Anodic oxide film as gate insulator for InP MOSFETs

An anodic oxide film of InP, which had an interface state density of ? 1011 cm?2 eV?1 near midgap and worked well as the gate insulator for InP MOSFETs, was obtained by optimising its preparation conditions. The excellence of the anodic oxide as a gate insulator was confirmed by a high electron effective mobility (1500 cm2/Vs) in the accumulation-mode InP MOSFETs.     

Thermally robust HfN metal as a promising gate electrode for advanced MOS device applications

A systematic study of thermally robust HfN metal gate on conventional SiO/sub 2/ and HfO/sub 2/ high-/spl kappa/ dielectrics for advanced CMOS applications is presented. Both HfN-SiO/sub 2/ and HfN-HfO/sub 2/ gate stacks demonstrates robust resistance against high-temperature rapid thermal annealing (RTA) treatments (up to 1000/spl deg/C), in terms of thermal stability of equivalent oxide thickness (EOT), work function, and leakage current. This excellent property is attributed to the superior oxygen diffusion barrier of HfN as well as the chemical stability of HfN-HfO/sub 2/ and HfN-SiO/sub 2/ interfaces. For both gate dielectrics, HfN metal shows an effective mid-gap work function. Furthermore, the EOT of HfN-HfO/sub 2/ gate stack has been successfully scaled down to less than 10 /spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability even after 1000/spl deg/C annealing, without using surface nitridation prior to HfO/sub 2/ deposition. As a result, the mobility is improved significantly in MOSFETs with HfN-HfO/sub 2/ gate stack. These results suggest that HfN metal electrode is an ideal candidate for ultrathin body fully depleted silicon-on-insulator (SOI) and symmetric double-gate MOS devices.     

Impact of dummy metal filling strategy dedicated to inductors integrated in advanced thick copper RF BEOL

A complete strategy to manage dummy fills inside a large spectrum of integrated RF inductors realized in an advanced thick copper RF back end of line (BEOL) is presented here. The main motivation of this paper is first to evaluate through a design of experiment (DOE) modeling, the impact on RF inductor performances of dummy metal fills inserted inside the coils, and then determine the right metal fill density to insert in order to be compliant with Digital metal density rules without degrading their electrical performances.     

Characterization issues of gate geometry in multifinger structurefor RF-SOI MOSFETs

In this letter, we propose that f_T and f_max properties in partially depleted SOI devices were analyzed in terms of gate electrode layout, body instability, and body resistance of multifinger structure. The speed characteristics were a strong function of the number of fingers and gate types such as T-gate and H-gate structures and were evaluated by g_m variation (Δg_m ), extra parasitic capacitance (ΔC_gs), and ac body instability     

Influence of body contact of SOI MOSFETs on the thermal conductance of devices

e of the body contact region to that of the body region is nearly equal to the ratio of the area. The use of an H shape gate body contact is suggested to aid power dissipation in SOI MOSFETs.     

SOI MOSFET的体接触对器件热导的影响

The thermal conductance of devices with different body contacts is studied. A new analytical expression is proposed. This expression can be used in parameter extraction, which gives both good efficiency and high precision. The ratio of thermal conductance of the body contact region to that of the body region is nearly equal to the ratio of the area. The use of an H shape gate body contact is suggested to aid power dissipation in SOI MOSFETs.     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

亚0.1μm高K栅介质MOSFETs的特性

用二维模拟软件 ISE研究了典型的 70 nm高 K介质 MOSFETs的短沟性能 .结果表明 ,由于 FIBL 效应 ,随着栅介质介电常数的增大 ,阈值电区减小 ,而漏电流和亚阈值摆幅增大 ,导致器件短沟性能退化 .这种退化可以通过改变侧墙材料来抑制     

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler-Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.     

Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.