A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3-μm technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time     

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word×1-b and 256 K word×4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7-μm double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 μm² and a chip size of 86.6 mm ². The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times     

High-voltage-tolerant I/O buffers with low-voltage CMOS process

This paper presents high-voltage-tolerant I/O buffer designs for a 1.9-V external cache interface and a 3.3-V system interface using 1.9-V MOS transistors in a 0.21-μm process with 40-Å gate-oxide thickness. Various circuit techniques are used for 1.9- and 3.3-V I/O buffers to ensure that the voltage across the gate oxide of every MOS element is below specified limits of 2.2 V for transient (short duty cycle) and 1.9 V for steady state. Only one PMOS pullup driver transistor between the bond pad and the power supply, and one NMOS pulldown driver transistor between the bond pad and ground, are used for the 1.9-V I/O buffer design, while cascoded MOS transistors between the bond pad and power supply or ground terminals are used for the 3.3-V I/O buffer design. The primary design goal is to ensure the reliability of MOS elements by avoiding excessive gate oxide stress due to high electric fields. However, due to differences in requirements for speed, power-supply voltage, and tristate leakage current, completely different circuit techniques have been used for the two designs. Both of the designs have been successfully implemented in a 400-MHz UltraSPARC microprocessor     

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

A 3.8-ns 16 K BiCMOS SRAM

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

A 45-ns 64-Mb DRAM with a merged match-line test architecture

A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm² has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm², and 30-fF cell capacitance has been achieved using an oxynitride layer (t_eff=5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-inself-test

An experimental 576 K BiCMOS emitter-coupled-logic (ECL)-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1 K on-chip logic gates to assist characterization, wafer testing, and package testing. The I/O is also transistor-transistor-logic (TTL) programmable with the first-metal mask     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devices

An experimental 11-ns 8 K×18 static RAM fabricated in a 1.2-μm CMOS technology with 0.5-μm channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V V_dd. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 μm² to yield a chip size of 60 mm²     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s     

3.3-V BiCMOS current-mode logic circuits for high-speed adders

New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-μm BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.