一款带8选1MUX的14位2.5GS/s D/A转换器

本文介绍了一款带8选1MUX的14位2.5GS/s D/A转换器。该转换器采用了“5+9”分段PMOS电流舵结构,偏置电路保证PMOS电流源阵列能够在PVT（温度、电源电压、工艺角）变化的条件下获得较大的输出阻抗。高速8to1 mux电路采用了3级结构,采用恰当的数据选择时序,提高了数据合成的可靠性。D/A转换器输入数据的高5位译码器中加入了DEM功能改善了D/A转换器模拟输出的动态性能。本文所述的带8选1MUX功能的14位2.5GS/s D/A转换器内嵌在一款高性能DDS电路中,流片的实测结果显示在时钟2.5GHz下, MUX和D/A转换器工作正常,输出信号在1GHz带宽范围内,SFDR> 40dB。与目前国际上已发表的非模拟重采样结构的D/A转换器（即没有采用“归零”或“四开关”这些模拟重采样结构）相比,本文介绍的D/A转换器具有较高的时钟频率（2.5GHz）和较好的高频SFDR性能(>40dB, up to 1GHz)。     

一款14位250MS/s采样率的电流舵数模转换器

A 14-bit 250-MS/s current-steering digital-to-analog converter(DAC) was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range(SFDR) is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero(TRI-DRRZ).Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.     

一种基于数字后台校准技术的14 bit 500 MS/s 数模转换器

Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

一种新颖的OTA结构的数模转换器

介绍了一种新颖结构的数模转换器，此转换器的设计核心是采用跨导运算技术，由CMOS运算跨导放大器（OTA）构成。此D／A转换器以模拟电流作为主要信号变量，以跨导运算放大器取代电压运算放大器，以基于OTA的有源元件取代部分无源元件，通过改变OTA的偏置电流，从而改变其互导增益gm和电压放大器增益Au，更适合于IC的集成。采用9个OTA构成一个8位的加法电路，8个OTA的互导增益gm对应8位的数字信号，8个MOS管作为开关运用由8位的数字信号控制，从而实现数字信号到模拟信号的转换。     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,设计了一种采用分段式电流舵结构的高速高精度DAC.电路设计中同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响.电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能.     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,本文设计了一种采用分段式电流舵结构的高速高精度DAC。同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响。电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能。     

带2位/级的新型转换过程和自锁定比较器的6位600 MS/s 逐次逼近型模数转换器

本文提出了一个在600MHz采样率下的6位逐次逼近寄存器（SAR）。由于对ADC高速的追求,本设计借鉴了2位/级的思想,并在此基础上给出了2位/级的新型转换过程,解决了DAC之间不匹配问题并减少了功耗。同时,采用了改进的分布式比较器拓扑结构以获得速度。通过整合多比较器的输入端减小了时钟馈通效应和失调,引入比较器的自锁技术进一步减小了功耗。测量结果表明,在600MHz采样频率、5.6MHz输入频率下,得到信号与噪声加失真比（SNDR）为32.13 dB,无杂散动态范围（SFDR）为44.05 dB。当输入频率接近奈奎斯特时,SNDR / SFDR分别下降到28.46/39.20 dB。最终该ADC由TSMC 65纳米工艺制造,其设计面积为0.045 mm2。在1.2V电源电压下的功耗为5.01 mW,并得到FoM值为252 fJ/转换过程。     

一种应用于可重构（WCDMA/TD-SCDMA/GSM）发射机的低功耗、三模sigma-delta数模转换器

本文提出了一种应用于软件无线电系统中无线发射机模块的,带通道滤波的多模式sigma-delta数模转换器。其转换频率、数字滤波器和sigma-delta调制器的传输函数,IDAC的位数和模拟重建滤波器的带宽都可以通过数字编程以满足WCDMA、TD-SCDMA和GSM协议的要求。芯片利用中芯国际0.13-μm CMOS工艺实现,有效面积为0.72mm2。在1.2V供电电压下,WCDMA/TD-SCDMA/GSM模式测试得到的功耗和SFDR分别为5.52/4.82/3.04 mW和62.8/60.1/75.5 dB。     

一种带12位3.2 MS/s 逐次逼近型模数转换器的电源线通信模拟前端电路

This paper presents an analog front end for a power line communication system,including a 12-bit3.2-MS/s energy-efficient successive approximation register analog-to-digital converter,a positive feedback programmable gain amplifier,a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators.A two segment capacitive array structure(6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements.Implemented in the GSMC 0.13 m 1.5 V/12 V dual-gate 4P6 M e-flash process,the analog front end occupies an area of 0.457 mm2 and consumes power of18.8 m W,in which 1.1 m W cost by the SAR ADC.Measured at 500 k Hz input,the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 d B and 60.60 d B respectively,achieving a figure of merit of 350 f J/conversion-step.     

A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.     

一种自校准的14-bit 100-MSPs 电流舵型DAC

本论文介绍了一种14-bit, 100MS/s CMOS数模转化器的设计与实现。引入了以模拟电流校准概念为基础模拟后台自校准技术。设计采用了恒定时钟负载开关驱动电路、校准周期随机化电路和输出自归零技术来提高DAC的动态性能。芯片利用中芯国际0.13-μm CMOS工艺实现,有效面积为1.33mm×0.97mm。数字和模拟电路分别在1.2/3.3V供电下工作,总的电流消耗为50mA。测试到的微分非线性和积分非线性分别为3.1LSB和4.3LSB。在100MHz采样频率,1MHz输入信号的工作条件下,测试得到的SFDR为72.8dB。     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC

This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It is based on a current steering binary weighted architecture and achieves 10-bit static linearity without calibration. Due to the use of a pseudo-segmented structure instead of a thermometer decoder, the operating speed of the converter can be up to 4.5 GS/s. The DAC occupies 0.4 mm $times$ 0.5 mm in a standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 36 dB has been measured over the complete Nyquist interval at sampling frequencies up to 3 GS/s. The power consumption at a 3 GHz clock frequency for a near-Nyquist sinusoidal output signal equals 29 mW .      

一种低功耗嵌入式14位400MHz数模转换器

设计了一个14位刷新频率达400MHz,用于高速频率合成器的低功耗嵌入式数模转换器。该数模转换器采用5+4+5分段式编码结构,其电流源控制开关输出驱动级采用归零编码以提高DAC动态特性。该数模转换器核采用0.18μm1P6M混合信号CMOS工艺实现,整个模块面积仅为1.1mm×0.87mm。测试结果表明,该DAC模块的微分非线性误差是-0.9～+0.5LSB,积分非线性误差是-1.4～+1.3LSB,在400MHz工作频率下,输出信号频率为80MHz时的无杂散动态范围为76.47dB,并且功耗仅为107.2mW。     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.