A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

The lateral super junction(SJ) power devices suffer the substrate-assisted depletion(SAD) effect,which breaks the charge balance of SJ resulting in the low breakdown voltage(BV).A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS).High density interface charges enhance the electric field in the buried oxide(BOX) layer to increase the block voltage of BOX,which suppresses the SAD effect to achieve the charge balance of SJ.In order to obtain the linear enhancement of electric field,SOI SJ-LDMOS with trenched BOX is presented.Because the trenched BOX self-adaptively collects holes according to the variable electric field strength,the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need.As a result,the charge balance between N and P pillars of SJ is achieved,which improves the BV of SJ-LDMOS to close that of the idea SJ structure.     

High voltage SOI LDMOS with a compound buried layer

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

具有复合k介质埋层的高压SOI器件解析模型

An analytical model for a novel high voltage silicon-on-insulator device with composite-k(relative permittivity) dielectric buried layer(CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k(k D 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage(BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional(2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI(LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.     

具有缓冲层和N型埋层的高压兼容Bi-CMOS工艺的超结LDMOS

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.     

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to $hbox{6} times hbox{10}^{6} hbox{V/cm}$, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 $muhbox{m}$ and drift length of 15 $muhbox{m}$ on a thin SOI substrate.      

具有增强介质层电场的SJ-LDMOS

横向超结功率器件遭受衬底辅助耗尽效应,这破坏了超结的电荷平衡,降低了器件的耐压。本文研究了一种基于增强介质层电场的解决方法,以提高横向超结器件（SJ-LDMOS）的耐压。通过高密度的界面电荷增强埋氧层（BOX）的电场从而提高埋氧层的耐压,这可以削弱纵向电场对超结的影响,消除衬底辅助耗尽效应,促进超结电荷平衡。为了获得理想的线性电场增强效果,一种具有槽形埋氧层的超结器件（TBOX SJ-LDMOS）被提出。槽形埋氧层能根据纵向电场的大小自适应地收集空穴,在埋氧层表面形成近似线性的电荷分布,这促进了超结的电荷平衡,提高了SJ-LDMOS器件的耐压,并使其接近理想超结的耐压值。     

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of E_I > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.     

A novel complementary N+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E1) and reduce the electric field of the silicon layer (Es), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a l-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E1 and reduced field Es by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.     

Super-High Breakdown Voltage (>1200V) SOI LDMOS with A Buried P-type Layer and A Thin BOX

为探索在薄埋氧层SOI衬底上实现超高耐压LDMOS的途径,提出了一种具有P埋层（BPL）的薄埋氧层SOI LDMOS结构,耐压1200V以上。该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层。当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降。采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1280V的耐压,将BOX层减薄到几百纳米以下又可以改善其热特性。