具有自动频率校准的宽频率范围Σ-Δ小数频率综合器

A wide range fractional-N frequency synthesizer in 0.18μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range.A 16-bit third-order sigma-delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm~2.The experimental results show the proposed frequency synthesizer consumes 4.3 raA from a single 1.8 V supply voltage except for buffers.The frequency range is 1.44-2.11 GHz and the frequency resolution is less than 0.4 kHz.The phase noise is -94 dBc/Hz @ 100 kHz and -121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz.The performance meets the requirements for the multi-band and multi-mode transceiver applications.     

一种宽带频率综合器快速自动频率校准技术

提出了一种新型快速自动频率校准技术,应用于宽带频率综合器的频带搜索和频率锁定过程。该自动频率校准模块通过直接控制频率综合器中压控振荡器(VCO)的开关电容阵列的闭合状态来调节VCO的振荡频率,实现快速锁定输出频率的目的。这种自校准技术由纯数字电路实现,校准过程只需5个时钟周期即可完成,时钟信号直接使用外部输入的参考时钟,具有算法简单、所需时钟周期少的优点。电路采用SMIC 0.18 μm CMOS工艺进行设计和验证,相比以往的校准技术,其校准时间明显减少。     

一款应用于无线通信的0.8~4.2 GHz单芯片全数字锁相环频率综合器

本文采用130nmCMOS工艺成功实现了应用于无线通信的0.8 - 4.2 GHz单片全数字锁相环频率合成器。文章提出了一系列的新方法,即采用了高频率分辨率的双带DCO以覆盖系统所需的2.5 GHz至5 GHz带宽;一个溢出计数器可以防止“pulse-swallowing”现象,显著减少了环路锁定时间;提出的NTW-clamp数字模块可以有效防止循环控制字的溢出;修改后的可编程分频器避免了传统架构中失败的边界操作。测量结果表明,该频率合成器的输出频率范围是0.8-4.2 GHz,锁定时间在2.68GHz减少了84%,最好的带内和带外相位噪声性能已达到-100 dBc/Hz,和-125 dBc/Hz,最低参考杂散达到-58dBc。     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

一种增益与频率成正比的双频段正交压控振荡器

This paper presents a novel dual-band quadrature voltage controlled oscillator(VCO) with the gain proportional to the oscillation frequency.Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration.Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO.The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived.For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with±16%variation over the entire frequency range.The phase noise is -138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and -137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.     

具有改进型自适应频率校准的快速锁定频率综合器

本文介绍了一种具有改进型自适应频率教准（AFC）模块的快速锁定锁相环型频率综合器,该综合器使用0.18ucm CMOS工艺实现。AFC的工作模式有两种：频率校准模式和存储/加载模式。频率校准模式使用了一种新型的鉴频器可以把频率校准时间缩短到16uS。在存储/加载模式下,通过保存频率校准后的结果并且在需要时加载,AFC可在1uS内使压控振荡器（VCO）的频率恢复为校准过的频率点。测试结果显示,VCO的谐振范围为620~920MHz;在环路带宽为10kHz时,锁相环带内噪声为-82dBc/Hz;频率校准模式下的锁定时间为20uS而存储/加载模式下为5uS;在1.8V供电下,锁定后频率综合器的工作电流为12mA。     

一种用于短距离无线通信并集成频率合成器的多模式多频带发射机

A reconfigurable multi-mode direct-conversion transmitter(TX) with integrated frequency synthesizer(FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and -126 dBc/Hz at a 1 MHz offset. The transmitter features a C10:2 dBm peak output power with a C9:5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.     

一种低功耗频率预置快速锁定的锁相环频率综合器

本文提出了一种2.4GHz低功耗频率预置快速锁定的锁相环频率综合器,该频率综合器使用0.18um 的CMOS 工艺制作。设计了低功耗的混合信号压控振荡器,双模预置分频器,数字处理器和非易失性存储器来降低整体系统的功耗和减小锁定时间。数字处理器可以在工艺偏差的情况下自动的校正压控振荡器的预置频率,使得对振荡器频率的预置可以达到很高的精度。测试结果表明,在1.8V 的电源电压下,频率综合器的电流消耗为4mA,它的典型的锁定时间小于3us。     

一种集成新型相位切换预分频器和高品质因素压控振荡器5 GHz CMOS频率综合器

本文实现了一种集成新型相位切换预分频器和高品质因素压控振荡器的锁相环频率综合器。该频率综合器在考虑噪声性能的基础上进行系统参数设计。预分频器采用了一种不易受工艺偏差影响的相位切换方式。对压控振荡器的电感开关电容和压控电容的品质因素进行了优化。与其他文献相比,该频率综合器使用相近的功耗取得更好的噪声性能。本文提出的频率综合器采用SMIC0.13微米工艺流片,芯片面积为11502500 μm²。当锁定在5 GHz时,其功耗在1.2V电源电压供电时为15mA。此时,1MHz频偏处相位噪声为-122.45dBc/Hz。     

适合宽输出范围频率综合器的CMOS压控振荡器电路

设计了一种基于锁相环宽输出范围(10～160M)的频率综合器,着重介绍了其中的压控振荡器(VCO)部分,采用单端、电流控制型的环振,使之在整个输出范围内,即0～1 20℃、工艺的ss～ffcorner,增益(Kvco.)的变化在3倍以内.无需根据输出频率对电荷泵的充、放电电流或环路滤波器中的电阻作不同设置,环路的衰减因子就可控制在可接受的范围内,并降低了对其它环路参数的要求.设计基于标准0.6μm N-WELL CMOS工艺,5V供电.     

用于无线传感器网络节点的小数分频频率综合器

This paper presents a fractional-N frequency synthesizer for wireless sensor network(WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop(PLL) based structure, which employs an LC voltagecontrolled oscillator(VCO) with small VCO gain(KVCO) and frequency step(fstep) variations, a charge pump(CP)with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups’ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 m CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86:34 d Bc/Hz at 100 k Hz offset and 114:17 d Bc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes’ requirements.     

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes the voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs by loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is -82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.     

一种适用于多带OFDM超宽带系统中的快速跳频3子带CMOS频率综合器

A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

ment shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 × 1.8 mm2.     

一种应用于GPS接收机的低功耗CMOS频率合成器

提出了一种应用于GPS/Galileo L1/E1波段接收机的低功耗频率合成器,并成功在0.18 µm CMOS 工艺中实现。通过在锁存器的输出端引入时钟控制管,高速源耦合逻辑预分频器相比传统结构,最高分频频率得到提高。测试结果显示,该频率合成器在1.8V的电源供电情况下消耗电流6 mA,带内相噪小于-87 dBc/Hz(15 KHz频率偏移处),杂散小于-65 dBc,核心电路面积0.6 mm2。