Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

MOSFET失配的研究现状与进展

特定工艺条件下的器件失配程度限制了射频／模拟集成电路的设计精度和成品率。电路设计者需要精确的MOSFET失配模型来约束电路优化设计,版图设计者需要相应的设计规则来减小芯片失配。本文介绍了MOSFET失配的基本概念;回顾了MOSFET模型的研究进展及相关的版图设计技术、计算机仿真方法;总结了MOSFET失酉己对电路性能的影响及消除技术。最后探讨了MOSFET失配的研究趋势。     

MOSFET器件并联实验研究

采用图腾柱的驱动方式,设计了应用于IXYS公司的功率MOSFET器件DE375-102N12的驱动电路。单个开关在多脉冲下具有良好的脉冲一致性。以该功率MOSFET器件进行的6个并联实验说明,影响并联的MOSFET的动态均流的主要参数是放电回路中的回路电感和寄生电感,电路板的布局与布线对并联的功率MOSFET有很大的影响,良好的布局可以大大提高电路的性能。     

Multisectional modeling of high-speed electrooptic modulators integrated in a microwave circuit CAD environment

We present a new multisectional model for high-speed electrooptic modulators, fully integrated within the framework of a microwave circuit computer-aided design (CAD) suite (MWOFFICE). Starting from geometrical and layout parameters, the model allows both simple (traveling-wave) and complex (phase reversal, periodically loaded) structures to be assembled, analyzed, and optimized from the standpoint of the electrical and electrooptic response (including chirp effects) both in small-signal (analog) and in large-signal (digital) operation, exploiting standard simulator tools. At no additional effort, parasitic and passive elements (such as optical or electrical delay paths) can be directly included in the modulator schematic, and the effect of transitions and package parasitics can be readily accounted for at a circuit level. Moreover, model integration within a circuit CAD suite enables one to seamlessly perform driver and modulator design and optimization within the same monolithic or hybrid circuit environment. Comparisons with experimental and literature data and design examples are presented to validate the approach and stress its potential in the design of high-speed electrooptic modulators.     

使用大规模存储器电路的PEX技术研究

随着集成电路(IC)制造工艺向深亚微米逐渐深入,寄生参数对IC的性能影响越来越大,因此对寄生参数的提取及分析(后仿真)也就显得愈发重要。文章以寄生参数提取的原理及基本方法为引入,分析寄生RC参数产生机制和计算方法,并以含有大规模存储单元的IC设计为例,研究如何利用现有的提取工具解决提取效率的问题,提出了模块划分、重复利用、参数定位和反标配置等操作方案,重点分析基于calibre XRC的PEX在IC设计中遇到的问题,并结合实际情况给出合适的解决方案。     

A design system for RFIC: challenges and solutions

The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having a good design methodology, innovation computer-aided design (CAD) tools, and a well-integrated design system are key factors for success. In this paper, we describe a design system developed to provide the designer with everything necessary to accurately predict the behavior of RFIC devices, including layout and package parasitic effects. We show how important a well-defined and integrated system is to manufacturing a design that meets specifications at the minimum cost, in the minimum time. A close link between schematic, models, and layout is of paramount importance to ensure the accuracy need for low-power RF design. We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success     

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.     

MOSFET模型＆参数提取

器件模型及参数作为工艺和设计之间的接口，对保证集成电路设计的投片成功具有决定意义。本文介绍了电路模拟中常用的几种MOSFET模型，并着重探讨了使用自动参数提取软件提取一套准确的模型参数的具体工作步骤。     

寄生电感对碳化硅MOSFET开关特性的影响

相比于传统的Si IGBT功率器件而言,碳化硅MOSFET可达到更高的开关频率、更高的工作温度以及更低的功率损耗.然而,快速的暂态过程使开关性能对回路的寄生参数更加敏感.因此,为了评估寄生电感对碳化硅MOSFET开关性能的影响,基于回路电感的概念,将栅极回路寄生电感、功率回路寄生电感以及共源极寄生电感等效成3个集总电感,并且从关断过电压、开通过电流及开关损耗等3个方面,对这3个电感对SiC MOSFET开关性能的影响进行了系统的对比研究.研究表明:共源极寄生电感对开关的影响最大,功率回路寄生电感次之,而栅极回路寄生电感影响最小.最后,基于实验分析结果,为高速开关电路的布局提出了一些值得借鉴的意见.     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

Applications of asynchronous circuits

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility (EMC) properties, and a natural match with heterogeneous system timing. In this overview paper each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. Conditions for applying asynchronous circuit technology, such as the existence and availability of computer-aided design (CAD) tools, circuit libraries, and effective test approaches, are discussed briefly. Asynchronous circuits do offer advantages for many applications, and their design methods and tools are now starting to become mature     

Study on the device characteristics of a quasi-SOI power MOSFETfabricated by reversed silicon wafer direct bonding

The device characteristics of a quasi-SOI power MOSFET were investigated to obtain its optimum device structure. The oxide at the original bottom surface of the bulk power MOSFET of the quasi-SOI power MOSFET formed by reversed silicon wafer direct bonding acts as the buried oxide of the conventional SOI power MOSFET. The short channel effect of the quasi-SOI power MOSFET was larger than that in the conventional SOI power MOSFET. It was suppressed by increasing the width of the oxide in the body region, and the parasitic bipolar effect was suppressed by decreasing it. We also propose a new device structure which can suppress the short channel effect and parasitic bipolar effect of a quasi-SOI power MOSFET based on the results of these experiments     

A comparative study of advanced MOSFET concepts

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 μm and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFET's parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed     

A new device design methodology for manufacturability

As future technology generations for integrated circuits continue to “shrink”, TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-μm MOSFET device are given to show the impact of device design procedures on device performance distributions and sensitivity variance profiles     

Relating statistical MOSFET model parameter variabilities to ICmanufacturing process fluctuations enabling realistic worst case design

The implementation of a viable statistical circuit design methodology requiring detailed knowledge of the variabilities of, and correlations among, the circuit simulator model parameters utilized by designers, and the determination of the important relationships between these CAD model parameter variabilities and the process variabilities causing them is presented. This work addresses the above requirements by detailing a new framework which was adopted for a 2-μm CMOS technology to enable realistic statistical circuit performance prediction prior to manufacture. Issues relating to MOSFET modeling, the derivation of fast “direct” parameter extraction methodologies suitable for rapid parameter generation, the employment of multivariate statistical techniques to analyze statistical parametric data, and the linking of the CAD model parameter variations to variabilities in process quantities are discussed. In this approach the correlated set of model parameters is reduced to a smaller and more manageable set of uncorrelated process-related factors. The ensuing construction and validation of realistic statistical circuit performance procedures is also discussed. Comparisons between measured and simulated variabilities of device characteristics is utilized to demonstrate the accuracy of the techniques described. The advantages of the proposed approach over more traditional “worst case” design methodologies are demonstrated     

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I-V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.     

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

Monte Carlo Static Timing Analysis with statistical sampling

With aggressive scaling of CMOS technologies, MOSFET devices are subject to increasing amounts of independent local statistical variability. The causes of these statistical variations and their effects on device performance have been extensively studied, but their impact on circuit performance is still difficult to predict. This paper proposes a method for modeling the impact of random intra-die statistical variations on digital circuit timing. The method allows the variation modeled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterization tools. By using statistical sampling techniques, we achieve close to the accuracy of full SPICE simulation, but with a computational effort similar to that of Statistical Static Timing Analysis, while removing some of the inaccurate assumptions of Statistical Static Timing Analysis.