MOSFET模型＆参数提取

器件模型及参数作为工艺和设计之间的接口，对保证集成电路设计的投片成功具有决定意义。本文介绍了电路模拟中常用的几种MOSFET模型，并着重探讨了使用自动参数提取软件提取一套准确的模型参数的具体工作步骤。     

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.     

An Assessment Methodology for Evaluating Communications Innovations

There has never been any shortage of ideas in the communications industry, only a problem of which to choose and which to reject. Building upon the thesis that to the extent a current innovation replicates the effects that past great innovations had on their host societies, an assessment tool is developed to aid in the design and decision processes. Three characterizations and two constraints are developed from an analysis of past great innovations that form the basis of the analysis technique. It has been found that this methodology can provoke new insights into old situations.     

An Improved Parasitic Parameter Extraction Method for InP HEMT

An improved parasitic parameter extraction method for InP high electron mobil-ity transistor(HEMT)is presented.Parasitic parameter extraction is the first step of model parameter extraction and its accuracy has a great impact on the subsequent internal pa-rameter extraction.It is necessary to accurately determine and effectively eliminate the parasitic effect,so as to avoid the error propagation to the internal circuit parameters.In this paper,in order to obtain higher accuracy of parasitic parameters,parasitic parameters are extracted based on traditional analytical method and optimization algorithm to obtain the best parasitic parameters.The validity of the proposed parasitic parameter extraction method is verified with excellent agreement between the measured and modeled S-param-eters up to 40 GHz for InP HEMT.In 0.1-40 GHz InP HEMT,the average relative error of the optimization algorithm is about 9%higher than that of the analysis method,which verifies the validity of the parasitic parameter extraction method.The extraction of parasit-ic parameters not only provides a foundation for the high-precision extraction of small sig-nal intrinsic parameters of HEMT devices,but also lays a foundation for the high-preci-sion extraction of equivalent circuit model parameters of large signal and noise signals of HEMT devices.     

精确的短沟MOSFET电路模型及参数提取

给出一套具有较高精度且同时适用于数字电路和模拟电路ＣＡＤ的短沟ＭＯＳ器件直流模型。该模型精确、高效，可移植到ＨＳＰＩＣＥ等通用线路分析软件中。结合解析和数值两种参数提取方法，文中采用局部优化参数提取法进行ＭＯＳ器件参数提取。优化算法采用单纯形直接搜索法。参数提取过程中考虑了输出电导的精确性。通过对１．２μｍＣＭＯＳ工艺ＮＭＯＳ器件的测试及参数提取，并进行模型计算，结果表明理论和实际值符合很好。     

超深亚微米集成电路互连线几何变异提取方法

硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键.这里基于电阻和电容等电学测试结构相应的数学计算公式,阐述进行互连线几何变异提取的方法,分析所采用的测试结构与计算公式的可行性,讨论误差来源,提出仿真工作与测试芯片设计原则.目的在于解决工艺建模与寄生参数建模过程中电阻和电容变异之间紧密的空间相关性,从而易于建立用于集成电路参数成品率评估计算的可制造性设计模型.     

Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements $C_{gc}(V_{g})$ to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers.      

Physical and CAD models for the implanted-channel VLSI MOSFET

A new approach is described for the modeling of practical MOS transistors that have nonuniform substrate doping profiles. The threshold characteristic is used to provide an accurate measure of body charge and thereby to give operating point dependences of the threshold voltage, body effect, mobility, and weak-inversion conduction. The results are incorporated into a simple and flexible CAD model suitable for existing and foreseeable devices. The model has continuity of current and all derivatives throughout all regions of operation. It provides an accurate representation of real transistors and minimizes numerical problems of convergence and stability. It has been implemented as level-4 in SPICE 2G.5 and is freely available for VLSI circuit design.     

A small geometry MOSFET model for CAD applications

A d.c. model for the CAD analysis of small geometry MOSFET's is presented. It includes the drain induced barrier lowering phenomena, the narrow channel effect and the hot carrier phenomena. A single current expression valid in continuous way over the entire range of operation, including the subthreshold and the saturation regimes, is provided.     

MOSFET modeling for analog circuit CAD: problems and prospects

The requirements for good MOSFET modeling are discussed, as they apply to usage in analog and mixed analog-digital design. A set of benchmark tests that can be easily performed by the reader are given, and it is argued that most CAD models today cannot pass all the tests, even for simple, long-channel devices at room temperature. A number of other problems are discussed, and in certain cases specific cures are suggested. The issue of parameter extraction is addressed. Finally, the context of model development and usage is considered, and it is argued that some of the factors responsible for the problems encountered in the modeling effort are of a nontechnical nature     

Parasitic Bipolar Junction Transistors in a Floating-Gate MOSFET for Fluorescence Detection

In this letter, we examined whether the parasitic bipolar junction transistors (BJTs) in the MOSFET fabricated by the standard CMOS process can play a role as a fluorescence detector. To suppress the action of two vertical parasitic BJTs, the gate and n-well were tied in the parasitic BJTs, and the body node was connected to the drain. The proposed device was compared with the inherent and the parasitic diodes in the MOSFET. It had 100 times higher photocurrents than the diodes in the MOSFET. In addition, it was applied for the detection of the fluorescent signal, and could detect near 10 nM of Alexa 546. Therefore, CMOS-process-compatible parasitic BJTs can be used as a photodetector in an integrated fluorescence detector.     

An Object Oriented Approach for Extraction Data from CAD Systems

1IntroductionThemostoftenuseddefinihonforthetermprocessplanningisthatitisconcernedwithdetendningthesequenceofprocessingandassemblystepsthatmustbeaccomplishedtomakeproducts.Theroutesheettypicallyliststheproduchonoperations,theirsequence,machinecellsorworkstationswhereeachoperationPerformed,fixtUresandtooling,andbinerequiredareforeachtask.Overtheyears,useofcomputersintheprocessplanninghasgeneratedconsiderableamountofinterests.Applicationofcomputersinprocessplainghasnotonlybeenasubjectofinterest…     

MOSFET器件后道封装测试中寄生电容的影响和解决方案

随着半导体后道封装测试的要求越来越高,其中对器件的测试判定已经不能简单的区分为“好”与“坏”来满足.后道封装测试应该尽可能实现准确的细化失效参数,从而给失效分析提供更快,更准确的判断.极大缩短从测试失效判定到失效原因分析,以及失效工艺改进的时间.鉴于金属氧化物半导体(MOSFET)的固有寄生电容效应,给后道封测失效判定...     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

一种专为IGBT和MOSFET设计的新型集成驱动器

介绍了一种专为IGBT和功率MOSFET设计的电力电子驱动器件———SCALE集成驱动器的性能特点和内部结构 ,给出了SCALE集成驱动器在中频臭氧发生器电源中的应用电路     

短沟道无结柱状围栅MOSFET的解析模型

通过在柱坐标系下求解二维泊松方程,建立了短沟道无结柱状围栅金属氧化物半导体场效应管的电势模型,并推导了阈值电压、亚阈值区电流和亚阈值摆幅的解析模型。在此基础上,分析了沟道长度、沟道直径和栅氧化层厚度等参数对阈值电压、亚阈值区电流和亚阈值摆幅的影响。最后,利用Atlas软件对器件进行了模拟研究。结果表明,根据解析模型得到的计算值与模拟值一致,验证了模型的准确性。这些模型可为设计和应用新型的短沟道无结柱状围栅金属氧化物半导体场效应管提供理论基础。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

RF集成电感的设计与寄生效应分析

分析了体硅 CMOS RF集成电路中电感的寄生效应 ,以及版图参数对电感品质因数 Q的影响 ,并通过Matlab程序模拟了在衬底电阻、金属条厚度、氧化层厚度改变时电感品质因数的变化 ,分析了不同应用频率时版图参数在寄生效应中所起的作用 ,得出了几条实用的设计原则并进行了实验验证 ,实验结果与模拟值符合得很好 ,表明此模拟方法与所得结论均可有效地用于指导射频 (RF)集成电路中集成电感的设计     

Statistical Models for Hot Electron Degradation in Nano-Scaled MOSFET Devices

In a MOS structure, the generation of hot carrier interface states is a critical feature of the item's reliability. On the nano-scale, there are problems with degradation in transconductance, shift in threshold voltage, and decrease in drain current capability. Quantum mechanics has been used to relate this decrease to degradation, and device failure. Although the lifetime, and degradation of a device are typically used to characterize its reliability, in this paper we model the distribution of hot-electron activation energies, which has appeal because it exhibits a two-point discrete mixture of logistic distributions. The logistic mixture presents computational problems that are addressed in simulation.