ESD issues for advanced CMOS technologies

As technologies advance towards the deep submicron, the ESD protection design issues have been known to become more critical. This paper examines the recent trends in ESD protection designs, the technology impact, and the specific approaches to build-in ESD reliability. It is shown that the efficient performance of advanced protection designs requires an optimized process that can meet the ESD robustness criterion.     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

Process influence on product CDM ESD performance

Effective ESD protection circuit design has become challenging due to rapid advances in process technology. This study was launched to address those concerns in deep sub-micron technologies and to look for a process windows that preserve CDM ESD robustness for a given ESD protection designs. Experimental results for 0.18 μm integrated CPU’s together with process window effects on CDM robustness are presented and discussed. The correlation between electrical characteristics and some of the common failure modes are described. It is shown that transistor off current lower than critical value can lead to degradation in time and an eventual secondary breakdown in a parasitic NPN transistor that results in unexpected CDM sensitivity.     

NMOS管Snapback特性ESD仿真模型研究

随着集成电路特征尺寸的不断缩小,ESD的问题始终困扰着芯片设计师们。文章提出了一种宏模型用于ESD的snapback仿真,它包含一个MOS管、一个NPN晶体管和一个衬底电阻,没有外部的电流源。简化的宏模型没有必要使用行为级的语言,如Verilog-A、VHDL-A。这使得仿真速度和收敛性得到提高。同时比较了三种先进的BJT模型:VBIC、Mextram、HICUM。模型参数可以通过模型参数提取软件(BSIMProPlus、ICCAP等)提取。     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors

Electrostatic discharge (ESD) failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. In general, the gate-to-contact spacing of salicided devices is known to have little impact on their ESD strength. However, experimental results presented in this paper show that the ESD strength depends on the gate-to-contact spacing independent of the silicided process. Subsequently, a detailed investigation of the influence of gate-to-source and gate-to-drain contact spacings is carried out for a salicided 0.13-/spl mu/m technology which provides new insight into the behavior of deep submicron ESD protection devices. It is shown that the reduction in current localization and increase in the power dissipating volume with increase in the gate-to-contact spacings are the primary causes of this improvement, which implies that even for silicided processes, the gate-to-contact spacing should be carefully engineered for efficient and robust ESD protection designs.     

一种改进的片内ESD保护电路仿真设计方法

对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.     

A new ESD protection structure for high-speed GaAs RF ICs

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 /spl Omega/ at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD.     

A novel vertical SCR for ESD protection in 40 V HV bipolar process

A vertical Silicon Controlled Rectifier (VSCR) realized in a high-voltage (HV) 40 V bipolar process is proposed for electrostatic discharge (ESD) protection applications. In addition, a new method is proposed to alter the layout of the emitter regions of the parasitic vertical PNP (VPNP) bipolar transistor in the VSCR to optimize the trigger voltage and the area of the VSCR. The transmission line pulsing (TLP) measurement results show that the VSCR possesses enhanced ESD robustness compared to the conventional vertical PNP (VPNP) bipolar transistor. The new VSCR can adjust trigger voltage, holding voltage and failure current with changing the number of emitter regions. Compare to VPNP bipolar transistor, the VSCR is more suitable for 40 V bipolar process.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Study of current saturation behaviors in dual direction SCR for ESD applications

The current saturation behaviors of Dual Direction Silicon Controlled Rectifier (DDSCR) and N+ Modified Dual Direction SCR (NMDDSCR) are investigated under transmission line pulse (TLP) stress, compared with Unidirectional SCR (USCR). DDSCR and NMDDSCR are more prone to saturation current state due to different ESD discharge paths, which are verified by TCAD simulation. The saturation current behavior should be suppressed for better ESD effectiveness and robustness. By increasing the lengths of N+ and P+ diffusion area, the saturation current can be suppressed effectively.     

Area-efficient layout design for CMOS output transistors

A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC's in high-density and high-speed applications     

Enhanced I ON/I OFF in ultra deep submicron CMOS devices using grooved nMOSFETs in comparison to planar nMOSFET

To manage the increasing static leakage in low power applications and reducing ON‐OFF current ratio due to scaling limitations, solutions for leakage reduction as well as improving the current drive of the device are sought at the device design and process technology levels. At the device design level, the important low power variables are the threshold voltage, the gate leakage current, the subthreshold leakage current and the device size. Grooved‐gate MOS devices are considered as the most promising candidates for use in submicron and deep submicron regions as they can overcome the short‐channel effects effectively. By varying the corner angle and adjusting other structural parameters such as junction depth, channel doping concentration, negative junction depth and oxide thickness, leakage current in nMOS devices can be minimised. In this article, 90, 80, 70, 60 and 50?nm devices are simulated using Devedit and Deckbuild module of Silvaco device simulator. The simulated results show that by changing the structural parameters, ON‐OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is drastically reduced, as well as applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this study.     

Lateral SCR devices with low-voltage high-current triggeringcharacteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6×60 μm² in a standard 0.6-μm CMOS technology without extra process modification     

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal–oxide–semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13- $muhbox{m}$ CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.      

A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD

Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on-chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.     

A novel SCR ESD protection for triple well CMOS technologies

A novel SCR structure for on-chip ESD protection implemented with a deep submicron triple well CMOS technology is presented. The triple well technology offers the possibility of biasing the p-well, on which the structure is built, under transient ESD stress conditions and independently from the substrate. This greatly affects the turn on mechanism of the structure. Unlike conventional SCR devices, the proposed p-well coupled SCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. The turn on of this structure is realized with a common RC trigger network. The concept is supported by device simulation results