Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.     

Active integrated antennas

Even with microwave techniques, however, signal losses in materials and decreased gain and power from solid-state devices become significant obstacles to creating low-cost, high-frequency wireless systems. Perhaps the most dramatic effect occurs when a circuit component becomes a significant fraction of a wavelength. At this point it may begin to function well as an antenna. For microwave and mm-wave signals, this can occur with circuits that are only centimetres in size. With conventional circuit techniques, this radiation may cause drastic signal losses, spurious coupling between circuit elements, and radio interference with other. However, with new techniques, it is possible to create circuits that use these effects to advantage. Known as active integrated antennas, these circuits have sparked interest as possible solutions to problems in designing the next-generation wireless systems. Active integrated antennas are a combination of solid-state devices and circuits with printed antenna structures. They comprise integrated radio-system elements that are fabricated using inexpensive printed-circuit techniques     

SG6849在单端反激式开关电源中的应用

SG6849芯片是SG(System General)公司生产的开关电源专用集成电路,使用该芯片设计小功率开关电源,可大大减少外围电路,降低成本,电路可靠性高,且可以不带副边反馈。详细介绍了SG6849芯片的工作原理,并基于此芯片设计了一个5.6W的单端反激式开关电源,给出了实验结果。     

A three-terminal piecewise-linear modelling approach to dc analysis of transistor circuits

The simulation of electronic circuits by computer has become an important part of present-day circuit analysis and design, especially in the area of integrated circuit design. One of the goals in computer simulation of integrated circuits is to have a program ‘package’ for which the input consists of chip fabrication data (mask dimensions, impurity profiles, material data such as carrier lifetimes) and the output displays the complete circuit response. This requires both an efficient modelling approach and a fast circuit analysis method. In this paper a simulation method is described which generates dc responses (in the form of operating points or transfer characteristics) of transistor circuits directly from physical parameter data. The basis of the method is a two-dimensional piecewise-linear approach to the dc modelling of bipolar transistors. The model is directly used in a piecewise-linear circuit analysis program to simulate the dc response of a given circuit.     

Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion.     

智能化断路器的开发

对智能化断路器的开发所涉及的关键技术进行分析和探讨。介绍一些基本的单元电路和相关技术,如单片机、专用集成电路、集成传感电源技术和系统集成化等,重点讨论了用于智能化断路器的智能化全功能低压脱扣器的开发,包括主要技术要求,总体结构和功能电路设计等。     

基于ATT7022B的交流配电柜设计

ATT7022B芯片是三相智能电表中专用集成芯片,使用该芯片设计交流配电柜监控系统,可大大减少外围电路,降低成本,电路可靠性高。详细介绍了ATT7022B的功能、特性,并基于此芯片设计了一款容量400A交流配电柜监控系统,并给出了交流配电柜监控系统框图和输入信号处理方法、实用电路以及设计注意事项等。     

Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

A general method for small-signal circuit analysis considering thermal effects

It is well known that the behaviour of integrated circuits is strongly affected by thermal feedback. A general method for evaluating, by linear analysis, the complete circuit performance is described that considers these effects. The procedure can easily be implemented using only well known computer programs for the circuit analysis. Simple models for a number of devices (diodes, transistors and f.e.t.s) used in integrated circuits are given. Examples, using the circuit-analysis program ECAP, are shown.     

基于序网等值电路的双馈风电机组接入系统短路电流计算方法

为了方便和准确地计算双馈风电机组(DFIG)接入系统的短路电流分布,提出了投撬棒后DFIG的工频和转频序网等值电路,并给出了利用该等值电路计算系统短路电流的方法。通过求解投撬棒后DFIG磁链的状态微分方程,得到其工频分量和转频分量的解析表达式。在此基础上,将DFIG的电压空间矢量方程按转频和工频分量进行分解,并根据空间矢量与相量间的关系,分别形成了转频和工频序网等值电路。其中,转频正序、负序等值电路分别为带内阻抗的电势和无源阻抗,而工频正序、负序等值电路均为无源阻抗。利用该等值电路只需已知DFIG的电机参数和故障初值条件而无需仿真即可求得DFIG接入系统各处的短路电流。以某DFIG接入系统为例,通过PSCAD仿真验证了该等值电路和短路计算方法在不同故障条件下的有效性。     

Undergraduate field applications engineers: a successful experimentin electronic design automation technology transfer

The United States has lost its leadership position in semiconductor manufacturing. It is, however, still dominant in the production of electronic design automation (EDA) software which supports semiconductor integrated circuit design and manufacturing. Research on EDA software is performed primarily in US universities. Early use of such software by the US semiconductor industry should constitute a precompetitive advantage that would help to compensate for the US's tack of competitiveness in manufacturing; however, because of the different natures of universities and industry, a significant technology transfer gap exists between them. Universities produce prototype software as research results, whereas the semiconductor industry would prefer to have robust rather than prototype versions. To bridge the gap, it has been proposed that the EDA industry be emulated and undergraduate engineering students used as field applications engineers (UFAEs). This paper describes a reasonably successful first attempt at this approach to EDA software technology transfer and discusses as well what could be done in the future to improve upon it     

3-D integration of RF circuits using Si micromachining

Micromachined silicon integrated circuits have the potential for providing an overarching circuit integration technology that can significantly reduce the size, weight, and cost of microwave and millimeter-wave components. The capability to integrate diverse substrate technologies opens the door for real multifunction chips, combining analog, digital, RF,and optoelectronic functions. This natural approach to three-dimensional (3-D) vertical integration not only can provide higher density circuits, but, by freeing RF circuit design from the tyranny of the two-dimensional (2-D) layout, can reach levels of performance not possible in a planar geometry. This article focuses on the concept of 3-D circuit integration using silicon (Si) bulk micromachining; however, similar techniques can be applied in any other III-V substrate material. Packaging issues prerequisite for the 3-D integration and component development that led to the capabilities for 3-D integration are discussed. The integration techniques are applied to a 3-D integrated W-band power cube, which provides a vehicle for successfully demonstrating the concept and basic techniques for 3-D integration. A concept study is presented of the use of micromachining to integrate Ka-band 2-D and 3-D corporate power combining architectures     

An Undergraduate Integrated Circuit Fabrication Laboratory

Over the last few years an integrated circuit fabrication laboratory intended primarily for use by undergraduates has been developed within the School of Electrical Engineering at Purdue University. Operating under the principle that integrated circuit design and laboratory practice are inseparable, the main objective was to allow the undergraduate student to acquire a working knowledge of how transistors, thin- and thick-film circuits, MOS field-effect transistors, and integrated circuits are fabricated. The emphasis is on how to fabricate the device in the laboratory and then to evaluate the device both electrically and metallurgically. This paper describes in detail how a device laboratory was organized for undergraduates with a minimal background in experimental technique.     

Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic

Alpha particles incident on CMOS integrated circuits deposit charges on circuit nodes resulting in single-event transients (SETs). These transient errors propagate through the circuit and reach a latch where they may get latched under proper conditions. This paper presents circuit design techniques to remove the effects of such SET pulses from the circuit. An optimized design is developed whose area, power, and speed performance is superior to other design methods for SET mitigation. Simulation results showing SET pulse elimination are presented.     

开关变换器中阵列式平面集成磁件的磁集成研究

阵列式磁芯结构使矩阵变压器具有多个磁路,本文以矩阵变压器的多磁路为基础,从磁路和电路的结合出发,提出在矩阵变压器上通过电路的有效组合并利用解耦集成方法集成电感,形成阵列式解耦集成磁件基本单元,并从整体磁路的角度分析了其解耦集成原理,给出其基本单元等效电路并进行了仿真。通过将该解耦集成磁件平面化,形成了阵列式平面集成磁件。将阵列式平面集成磁件应用到带变压器隔离的Cuk变换电路的实验研究表明,阵列式平面集成磁件的平面化和阵列式结构使其达到了轻、小、薄的目的,并降低了损耗,并证明本文提出的阵列式平面集成磁件具有良好的性能。     

采用PLX9054和51单片机PCI板卡设计

PCI总线接口芯片PLX9054，可工作于主、从两种方式。PLX9054提供了多数主流RISC 32位CPU的无缝接口电路设计，但在实际工作中，可能板卡工作在较慢速的数据采集或通讯状态，用51单片机就能满足。然而，用51单片机作为PLX9054的本地CPU与PLX9054互连需要复杂的接口电路设计。文中采用了一种实际且简便的电路方案，解决了这一问题。     

An Economy Integrated Circuits Laboratory

The high cost of establishing and maintaining an integrated circuit fabrication facility is prohibitive for many electrical engineering programs. As discussed in this paper, an integrated circuit laboratory experience can be realized for a total investment of less than $ 5000. The laboratory is based upon the monolithic integrated circuit breadboards commercially available, and requires a lead bonder for interconnecting elements on the breadboard chips. Characteristics and limitations of monolithic structures are readily studied in this laboratory, and student-generated custom-designed circuits are easily assembled.     

多路隔离输出全数字伺服系统开关电源设计

根据设计全数字永磁交流伺服系统的需要,使用Power Integration公司生产的开关电源专用集成芯片TOP224Y,设计了单端反激式多输出辅助开关电源。使用该芯片设计的小功率开关电源,可大大减少外围电路,降低成本,提高可靠性,同时,可以改善电源的电磁兼容性能。重点论述了开关电源的电路设计及高频变压器的设计。本辅助电源稍经改动也可以直接用在其他电机控制系统中。