Rework techniques process evaluation for chip scale packages

The packaging formats, chip scale package (CSP) and ball grid array (BGA) have allowed significant reductions in component size compared to conventional surface mount devices (SMD) such as quad flat packs (QFP). However, the position of the solder joints formed (underneath the chip) after reflow means that visual inspection is impossible. For the defective chip, the only realistic method of rework is to remove and replace it. Component removal can be easily achieved, however replacement may be more complex. Difficulties in the procedure may arise from loss of terminations during the removal process, and high component population densities on printed circuit boards (PCB) may also inhibit access to the component pad site. The typical rework process consists of a number of steps including; component removal, PCB pad clean-up, flux or solder paste application, component placement and reflow. In this paper, we evaluate the pad clean up stage of the CSP rework process, including the design and analysis of a variety of solder paste or flux deposition techniques. Two PCB pad-cleaning methods have been compared and conclusions drawn from the resultant pad finish. Four deposition techniques have been assessed; these include mini-stencil, dip transfer, on- and off-contact stamping. Mini-stencil is the traditional method used in the electronics manufacturing industry for the deposition of solder paste onto reworked component sites. The remaining deposition techniques have been developed in order to overcome access restrictions that might exist on densely populated PCB's     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.     

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Solder joint fatigue models: review and applicability to chip scale packages

A review of fourteen solder joint fatigue models is presented here with an emphasis on summarizing the features and applications of each fatigue model. The models are classified into five categories: stress-based, plastic strain-based, creep strain-based, energy-based, and damage-based. Fatigue models falling outside these categories are categorized as ‘other empirical models’. Each model is presented under one category with the relevant parameters and applicable packages. Following each category, common issues such as thermal cycling conditions, solder joint geometry, and coverage are addressed. Two fatigue model application scenarios are discussed. In the first scenario, a set of existing fatigue test data is given to the engineer who must determine how best to interpret the data and which fatigue model(s) best apply. In the second scenario, a test scheme must be devised for a new chip scale package product. The number of cycles to failure (N_f) or fatigue life must be determined. A general procedure is presented for choosing an appropriate fatigue model(s) based on the package conditions and limited Finite Element Analysis time. This procedure is summarized in a flowchart.     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.     

Interfacial reaction and solder joint reliability of Pb-free solders in lead frame chip scale packages (LF-CSP)

Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To evaluate the various solder balls in CSP package applications, Pb-free Sn-Ag-X (X=In, Cu, Bi) and Sn-9Zn-1Bi-5In solder balls were characterized by melting behavior, phases, interfacial reaction, and solder joint reliability. For studying joint strength between solders and under bump metallurgy (UBM) systems, various UBMs were prepared by electroplating and electroless plating. After T/C (temperature cycle) test, Sn3.5Ag8.5In solder was partially corroded and its shape was distorted. This phenomenon was observed in a Sn3Ag10In 1Cu solder system, too. Their fractured surface, microstructure of solder joint interface, and of bulk solder ball were examined and analyzed by optical microscopy, SEM and EDX. To simulate the real surface mounting condition and evaluate the solder joint reliability on board level, Daisy chain test samples using LF-CSP packages were prepared with various Pb-free solders, then a temperature cycle test (−65∼ 150°C) was performed. All tested Pb-free solders showed better board level solder joint reliability than Sn-36Pb-2Ag. Sn-3.5Ag-0.7Cu and Sn-9Zn-1Bi-5In solders showed 35%, 100% superior solder joint reliability than Sn-36Pb-2Ag solder ball, respectively.     

基于F型管壳的旋转缝焊技术研究

本文深入研究了旋转缝焊技术,讨论了缝焊中焊边受力、速度变化和热量分布情况,分析了影响旋转缝焊气密性的主要因素.     

Mechanical fatigue test method for chip/underfill delamination in flip-chip packages

Underfill resin between Si chips and printed circuit boards is useful for improving the reliability of flip-chip packages. Generally, thermal cycle tests (TCTs) are applied to electronic packages under development in order to prove their reliability. At the early stage of development, however, a more effective test method is desirable, because TCTs are time-consuming. A new mechanical fatigue test for the underfill resin in flip-chip packages, namely the four points support test method, is proposed in this paper. The validity of the mechanical test method could be verified from the results of stress analyses and experiments. Considering the chip/underfill delamination statistically based on the assumption of Markov process, it was shown that the delamination probability during cyclic loads could be estimated with equations of the displacement range and number of cycles.     

Failure mechanism of lead-free solder joints in flip chip packages

The failure mechanisms of SnAgCu solder on Al/Ni(V)/Cu thin-film, underbump metallurgy (UBM) were investigated after multiple reflows and high-temperature storage using a ball shear test, fracture-surface analysis, and cross-sectional microstructure examination. The results were also compared with those of eutectic SnPb solder. The Al/Ni (V)/Cu thin-film UBM was found to be robust enough to resist multiple reflows and thermal aging at conditions used for normal production purposes in both SnAgCu and eutectic SnPb systems. It was found that, in the SnAgCu system, the failure mode changed with the number of reflows, relating to the consumption of the thin-film UBM because of the severe interfacial reaction between the solder and the UBM layer. After high-temperature storage, the solder joints failed inside the solder ball in a ductile manner in both SnAgCu and SnPb systems. Very fine Ag₃Sn particles were formed during multiple reflows in the SnAgCu system. They were found to be able to strengthen the bulk solder. The dispersion-strengthening effect of Ag₃Sn was lost after a short period of thermal aging, caused by the rapid coarsening of these fine particles.     

Vapour microcell for chip scale atomic frequency standard

Reported is the original implementation of a microcell (1 mm³ ) in which a stable cesium vapour is generated after the cell is sealed. This new type of microcell is suitable for chip scale atomic clocks (CSACs) and can be realised at the industrial scale in an economic way     

Thermal resistance analysis and validation of flip chip PBGA packages

This work proposes a finite element numerical methodology to predict the thermal resistance of both flip chip-plastic ball grid array (FC-PBGA) with a bare die and FC-PBGA with a metal cap. The 3D finite element model was initially constructed to simulate the thermal resistance of FC-PBGA. A thermal resistance experiment was performed to verify the FEM results, following the construction of specimens of FC-PBGA with a bare die and with an aluminum cap, using six-layered substrate. The verified finite element model was employed to determine the thermal resistance of FC-PBGA with a copper cap using four-layered and six-layered substrates. Experimental results demonstrated that FC-PBGA with a metal cap improves thermal performance by 35% over with a bare die. FC-PBGA with a copper cap slightly improves thermal performance from 2% to 2.8% over that of FC-PBGA with an aluminum cap. The thermal resistance of FC-PBGA with a four-layered substrate is reduced by 4.0% to 5.9% from that of FC-PBGA with a six-layered substrate, since the four-layered substrate contains less metal. The finite element numerical results negligibly differ from the experimental results by 6% to 8.1%. A finite element numerical methodology is here proposed to predict the thermal resistance of FC-PBGA. The methodology is effective in researching and developing new products or improving existing packages.     

A performance and manufacturability evaluation of bump chip carrier packages

Bump chip carrier [(BCC) registered trademark of Fujitsu Ltd.] is an attractive solution to the demand of high packaging density of low input/output (I/O)-count packages. In this paper, an extensive finite element thermomechanical analysis has been conducted to evaluate the reliability of BCC packages, both with and without heat slugs, during thermal cycling. The effect of a variety of parameters on package reliability has been evaluated, including board thickness, package size mold material, solder paste thickness, and terminal height. The solder reliability of corner leads versus inner leads, as well as square leads versus rectangular leads has also been investigated. During manufacturing, molded panels for BCC packages undergo significant warpage. Two types of mold designs are compared through three-dimensional finite element analysis. A variety of mold compound materials have been evaluated. The most effective ways to reduce manufacturing-induced warpage have been suggested.     

An analysis of the thermal response of power chip packages

Since power densities in integrated circuits and power semiconductor devices are continuously increasing due to miniaturization of circuitry, the design of optimum heat spreaders and heat sinks for these applications requires rather sophisticated calculational methods. The chips and spreaders are usually rectangular in shape and although the problem is three-dimensional in nature, it is usually approximated by two-dimensional configurations. Steady-state and transient analytic solutions are presented for the axisymmetric, two-dimensional, and three-dimensional spreader geometries, which can be used to calculate the thermal resistance of the base alone. To determine the thermal resistance of the chip-base combination, the one-dimensional chip thermal resistance should be added to that of the base. These analytic solutions provide calculational means which are easier than the numerical methods. The exact analytic steady-state and transient solutions developed for the axisymmetric, two-dimensional, and three-dimensional configurations are in excellent agreement with the numerical calculations. The parametric calculations provide information on the important guidelines that a packaging engineer should bear in mind while designing and optimizing heat spreaders for power semiconductor applications. These points can be summarized as follows: 1) for a given chip area there exists an optimal base area, 2) increasing the base thickness initially decreases the thermal resistance and beyond a certain limit the latter increases with base thickness, and 3) the convective heat transfer coefficient strongly affects the thermal resistance and the usual assumption of an isothermal base is not always appropriate.     

Self-adaptive phosphor coating technology for wafer-level scale chip packaging

A new self-adaptive phosphor coating technology has been successfully developed,which adopted a slurry method combined with a self-exposure process.A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity.The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a waferlevel scale phosphor conformal coating.The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.     

Wafer-level chip scale packaging: benefits for integrated passivedevices

Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost