Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Prediction of plasma charging induced gate oxide damage by plasmacharging probe

The plasma processing induced wafer charging damage is predicted by the newly developed SPORT (Stanford Plasma On-wafer Real Time) charging probe. Such a probe can directly measure the spatial charging voltage built up on a wafer surface as well as the charging current from the plasma. Both antenna dependence of damage and charge fluence through a gate oxide due to charging can be calculated from the intersection between plasma I-V characteristic measured by the probe and intrinsic MOS I-V characteristic. This result agrees well with the real MOS capacitor damage data from O₂ plasma processing. Thus, given a fluence criteria, this methodology gives a means for predicting the minimum antenna ratio for observable damage     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

A model and experiments for thin oxide damage from wafer chargingin magnetron plasmas

A physically based model that has been developed to explain the role of plasma nonuniformity in charge damage to oxides is presented. For a uniform plasma the local conduction currents to the water surface integrate to zero over the RF period, and the surface charging is sufficient to damage oxides. For the case of thin oxides under a gate exposed to a nonuniform magnetron plasma, the gate surface can charge up until the oxide tunneling current balances the difference in the mean local conduction currents from the plasma. It is this oxide current that leads to degradation. The oxide current obtained via SPICE circuit simulations, probe measurements and breakdown measurements shows good agreement with experimental damage data of `antenna' capacitors     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Thin-oxide damage from gate charging during plasma processing

The plasma-induced charge damage to small gate gate MOS capacitors is investigated by using `antenna' structures. After an O₂ plasma step the interface state density increases with increasing antenna area and varies by two orders of magnitude. A hole trapping-induced breakdown mechanism during plasma charging is supported by experimental evidence which includes annealing and polarity effects for charge to breakdown and tunneling currents. In addition, oxide susceptibility is shown to depend on oxide growth conditions and is predictable by negative bias-temperature aging     

A mechanism of gate oxide deterioration during As+ ionimplantation

The deterioration or catastrophic breakdown of thin gate oxides during ion implantation is studied. The effect of ion beam density, the distribution of the gate oxide deterioration over a wafer, and the effect of photoresist coverage are shown quantitatively by measuring the number of interface states generated in MOS capacitors. It is shown that the four charge sources contribute to the deterioration of gate oxide: the irradiated ion beam, the secondary electrons emitted from the gate electrode, the charges accumulated on the photoresist surface around the gate electrode, and the secondary electrons emitted from a wafer holder. The first three charges accelerate the deterioration of the gate oxide and the last one reduces it. A model of the gate oxide deterioration in ion implantation that is very useful for finding methods of reducing the charging damage is presented     

Degradation and breakdown of thin silicon dioxide films underdynamic electrical stress

Thin oxide MOS capacitors have been subjected to dynamic voltage stresses of different characteristics (shape, amplitude and frequency) in order to analyze the transient response and the degradation of the oxide as a function of the stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. As for the oxide degradation, the experimental data has been interpreted in terms of a phenomenological model previously developed for dc stresses. According to this model, the current evolution in voltage stresses is assumed to be related to the oxide wearout. The evolution of the current during bipolar voltage stresses shows the existence of two different regimes, the degradation being much faster at low frequencies than at high frequencies. In both regimes, the frequency dependence is not significant, and the change from one regime to the other takes place at a threshold frequency which depends on the oxide field. These trends are also observed in time-to-breakdown versus frequency data, thus suggesting a strong correlation between degradation and breakdown in dynamic stresses. The experimental results are discussed in terms of microscopic degradation models     

Oxide damage from plasma charging: breakdown mechanism and oxidequality

The plasma-induced charge damage to small gate area MOS capacitors is investigated by using “antenna” structures. Here, we focus on the oxide defect characterization in a single wafer asher, and the role of oxide quality in a parallel plate etcher. The observed damage includes early breakdowns, excessive leakage current, an increase in interface states, and a decrease in charge-to-breakdown value. Moreover, annealing and polarity results support a hole trapping model for damage. In addition, it was found that the percentage of breakdown failure increases as the oxide quality decreases, In particular, the observed damage can increase up to 30 times when the initial oxide is degraded before plasma exposure according to how the oxide is prepared and annealed. This is important since it helps to explain how different process steps interact to affect the final yield. For instance a previous plasma process step may degrade an oxide and make it much more susceptible to damage by a subsequent plasma step     

Oxide thickness dependence of plasma charging damage

Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q_bd) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180°C) conditions. As the oxide thickness is thinned down below 3 nm, the Q_bd becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage.     

Plasma charging damage on ultrathin gate oxides

Capacitor C-V and threshold voltage and subthreshold swing of MOSFET's with gate oxide thickness varying from 2.2 to 7.7 nm are analyzed to study the plasma charging damage by the metal etching process. Surprisingly, the ultrathin gate oxide has better immunity to plasma charging damage than the thicker oxide, thanks to the excellent tolerance of the thin gate oxide to tunneling current. This finding has very positive implications for the prospect of manufacturable scaling of gate oxide to very thin thickness     

Simplified quantitative stress-induced leakage current (SILC) model for MOS devices

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

A novel technology to reduce the antenna charging effects duringpolysilicon gate electron-cyclotron-resonance etching

A novel technique, which uses Cl₂/O₂ mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl₂ /O₂ can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E_bd degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl₂/O₂ mixed gas     

Simulating process-induced gate oxide damage in circuits

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator     

A comparative analysis of substrate current generation mechanisms in tunneling MOS capacitors

This paper presents a critical analysis of the origin of majority and minority carrier substrate currents in tunneling MOS capacitors. For this purpose, a novel, physically-based model, which is comprehensive in terms of impact ionization and hot carrier photon emission and re-absorption in the substrate, is presented. The model provides a better quantitative understanding of the relative importance of different physical mechanisms on the origin of substrate currents in tunneling MOS capacitors featuring different oxide thickness. The results indicate that for thick oxides, the majority carrier substrate current is dominated by anode, hole injection, while the minority carrier current is consistent with a photon emission-absorption mechanism, at least in the range of oxide voltage and oxide thickness covered by the considered experiments. These two currents appear to be strictly correlated because of the relatively flat ratio between impact ionization and photon emission scattering rates and because of the weak dependence of hole transmission probability on oxide thickness and gate bias. Simulations also suggest that, for thinner oxides and smaller oxide voltage drop, the photon emission mechanism might become dominant in the generation of substrate holes.     

Plasma-parameter dependence of thin-oxide damage from wafercharging during electron-cyclotron-resonance plasma processing

In this work, the effects of plasma-parameter variations on the charging damage of polysilicon-gate MOS capacitor test structures exposed to O₂ electron-cyclotron-resonance (ECR) plasmas are investigated. The results show that charging damage is generated when large potential differences exist across the gate-oxide layers of the MOS capacitor test structures and that these potential differences can only occur in the presence of plasma nonuniformities. These results demonstrate the critical need for plasma uniformity during processing, in particular as device dimensions shrink and gate-oxide thicknesses decrease. The plasma parameters were varied by adjusting the neutral gas pressure and by independently biasing a circular grid and a ring electrode located above the wafer. The damage induced in the test wafers during the plasma exposure was characterized with ramp-voltage breakdown measurements. Radial profiles of the floating potential measured with a Langmuir probe were found to vary nonuniformly when the grid electrode was positively biased due to preferential depletion of electrons relative to ions beneath the grid electrode. An equivalent-circuit model of the test wafer and the wafer-stage electrode predicts that the silicon substrate acquires a potential equal to the average of the wafer surface potential. Comparisons of the calculated profiles of the potential difference across the gate-oxide layers of the test structures and whole-wafer maps of the breakdown-voltage measurements show that the majority of the damage occurs where the oxide potential difference is largest and that the damage only occurs in the presence of plasma nonuniformities