On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

一种具有动态零点补偿的电流模DC-DC降压型转换器

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm~2.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.     

Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-level RHBD(radiation-hardening by design) techniques were employed.Adaptive slope compensation was used to improve the inherent instability.The H-gate MOS transistors,annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose.A boost converter was fabricated by a standard commercial 0.35μm CMOS process.The hardened design converter can work properly in a wide range of total dose radiation environments,with increasing total dose radiation.The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

基于电流型DC-DC变换器建模与分析

为了推导建立电流型DC-DC变换器系统传递函数,采用电路平均法的处理方式对电流型正激DC-DC变换器进行平均和线性化处理,得到小信号等效电路模型,给出系统框图。应用网络分析仪Agilent4395A实测电路传递函数给出Bode图,从而去验证建模仿真的正确性。改变电路参数进一步验证建模仿真的通用性。实验结果验证了利用电路平均法得到的电流型DC-DC变换器模型的正确性和通用性。     

A DC-DC converter for short-channel CMOS technologies

An integrated DC-DC converter with two passive external components was designed and fabricated in an advanced, short-channel (L_eff <0.2 μm, V_dd<2 V) CMOS technology. This design was undertaken to examine the feasibility of implementing an inductive buck converter with passive components small enough to fit entirely within a packaged chip. High switching frequencies (>10 MHz) were used to minimize the size of external components, and novel circuits were used to reduce the stress on the short channel devices. Measured efficiencies for a 3.3 V to 1.65 V converter were approximately 75% for output currents from 15 to 40 mA     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

A CMOS oversampling D/A converter with a current-mode semidigitalreconstruction filter

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm² when integrated in a 1.2-μm digital CMOS technology     

带有高精度片上电流感应器的自适应开关频率降压型DC-DC变换器

本文提出了一种基于电流模式的PWM降压型DC-DC变换器。在高精度片上电流感应器的作用下,当负载不同时自动选择开关频率,提高了系统效率,并获得良好的瞬态响应。电流感应器采用简单的开关技术省去了复杂的运算放大器,但获得了高精度,减少了功率损耗,节省了芯片面积。此外,为了避免启动时的浪涌电流,设计了一种新型的软启动电路。芯片采用了0.5μm标准CMOS工艺,面积3.38mm2,电流感应器的精度可以达到99.5%@200mA,在5-18V的宽输入电压范围内可以输出2A的负载电流。     

A common-gate bootstrapped CMOS rectifier for VHF isolated DC-DC converter

A common-gate bootstrapped CMOS rectifier dedicated for VHF (very high frequency) isolated DC-DC converter is proposed.It uses common-gate bootstrapped technique to compensate the power loss due to the threshold voltage,and to solve the reflux problem in the conventional rectifier circuit.As a result,it improves the power conversion efficiency (PCE) and voltage conversion ratio (VCR).The design saves almost 90% of the area compared to a previously reported double capacitor structure.In addition,we compare the previous rectifier with the proposed common-gate bootstrapped rectifier in the case of the same area;simulation results show that the PCE and VCR of the proposed structure are superior to other structures.The proposed common-gate bootstrapped rectifier was fabricated by using CSMC 0.5 μm BCD process.The measured maximum PCE is 86% and VCR achieves 77% at the operating frequency of 20 MHz.The average PCE is about 79% and average VCR achieves 71% in the frequency range of 30-70 MHz.Measured PCE and VCR have been improved compared to previous results.     

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

An oversampling bandpass digital-to-analog converter has been designed so as to eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel mismatch in wireless transmitters. The converter combines a cascaded noise-shaping sigma-delta (/spl Sigma//spl Delta/) modulator with digital finite impulse response (FIR) and mixed-signal semi-digital filters that attenuate out-of-band quantization noise. The performance of the converter in the presence of current source mismatch has been improved through the use of bandpass data weighted averaging. An experimental prototype of the converter, integrated in a 0.25-/spl mu/m CMOS technology, provides 83 dB of dynamic range for a 6.25-MHz signal band centered at 50 MHz, and suppresses out-of-band quantization noise by 38 dB.     

A novel technique for the on-chip tuning of monolithic filters

Monolithic analog filters, with the exception of switched capacitor filters need on-chip tuning. Existing schemes of PLL and master-slave techniques use phase control for tuning. The proposed method uses amplitude detection, where the reference voltage itself is derived from the input. Much work has recently been done on active RC continuous-time filters in VLSI [4]-[8]. The heart of all such systems is an integrator with a voltage-variable time-constant (VVI). To generate the control for the VVI, these schemes use either a self-tuning filter (follow the master technique) [5] or a phase-locked loop [8], locking on to a stable reference frequency. Unlike these techniques which are essentially phase-control schemes, what is proposed here is a gain-control scheme.     

峰值电流型PWM调制buck DC-DC的建模与仿真分析

针对目前直流转直流(DC-DC)变换器系统建模方法受限于实际电路的局限性,提出了一种新型的Cadence系统建模方法。利用Cadence工具及其理想元器件,建立脉宽调制(PWM)峰值电流型buck DC-DC的系统模型。为验证模型的性能,在旺宏0.5 μm BCD工艺条件下,用电路结构替换理想模型,得到电路系统,并将其与系统模型的仿真结果进行对比。仿真结果表明,以该系统模型为指导设计的buck DC-DC芯片在340 kHz工作频率下具有宽输出电压范围,并能提供2 A的大负载电流,从而验证了该设计方法的可行性。     

A current-mode buck DC-DC controller with adaptive on-time control

A current-mode buck DC-DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback, and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed, but also achieves the independence of loop stability on output capacitor ESR. In addition, the AOT current-mode control does not have subharmonic oscillation phenomenon seen in fixed frequency peak current-mode control, so there is no need of the slope compensation circuit. The auto-skip pulse frequency modulation (PFM) mode improves the conversion efficiency of light load effectively. The controller has been fabricated with UMC 0.6-μm BCD process successfully and the detailed experimental results are shown.     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

1.5-V current-mode CMOS true RMS-DC converter based on class-AB transconductors

A current-mode CMOS RMS-DC converter is presented. The basic building blocks are based on a novel approach to design current-mode computational cells. In such an approach, the large-signal V-I characteristic of class-AB transconductors is conveniently exploited leading to a very regular and compact implementation. A proper biasing scheme in such transconductors allows operation with supply voltage as low as V/sub GS/+2V/sub DSsat/. Measurement results from a practical prototype are presented in order to demonstrate the technique proposed here.     

高压大电流单片DC/DC的抗总剂量加固技术

采用电流模、电压模双环控制结构,结合峰值电流采样等关键技术,实现了一款功率集成的单片DC/DC变换器。设计的峰值电流采样、斜率补偿大大提高了系统的稳定性,提高了系统的快速瞬态响应能力;针对高压低压差线性稳压器(LDO)、电流采样等高压模块电路,通过采样齐纳二极管、高压NJFET代替高压厚栅MOSFET等的设计方法,从总体上降低高压器件的数量,在基于30 V BCD(Bipolar-CMOS-DMOS)工艺上,结合特殊器件的版图设计方法,制作出一款输入电压5.5~17 V,电压调整率小于10 mV,电流调整率小于25 mV,输出电流大于5 A,系统静态电流小于25 mA,最高工作效率为93%的高效单片DC/DC,其抗总剂量能力大于100 krad(Si)。     

A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies

A 1-V integrated CMOS current-mode boost converter implemented in a standard 3.3/5-V 0.6-/spl mu/m CMOS technology (V/sub TH//spl ap/0.85 V), providing power-conversion efficiency of higher than 85% at 100-mA output current, is presented in this paper. The high-performance boost converter is successfully developed due to three proposed low-voltage circuit structures, including an inductor-current sensing circuit for current-mode operation with accuracy of higher than 94%, a precision V-I converter for compensation-ramp generation in current-mode control, and a VCO providing supply-independent clock and ramp signals. Moreover, a proposed startup circuit enables proper converter startup within a sub-1-V supply condition.     

A new ZVT-ZCT-PWM DC-DC converter

In this paper, a new active snubber cell is proposed to contrive a new family of pulse width modulated (PWM) converters. This snubber cell provides zero voltage transition (ZVT) turn on and zero current transition (ZCT) turn off together for the main switch of a converter. Also, the snubber cell is implemented by using only one quasi resonant circuit without an important increase in the cost and complexity of the converter. New ZVT-ZCT-PWM converter equipped with the proposed snubber cell provides most the desirable features of both ZVT and ZCT converters presented previously, and overcomes most the drawbacks of these converters. Subsequently, the new converter can operate with soft switching successfully at very wide line and load ranges and at considerably high frequencies. Moreover, all semiconductor devices operate under soft switching, the main devices do not have any additional voltage and current stresses, and the stresses on the auxiliary devices are at low levels. Also, the new converter has a simple structure, low cost and ease of control. In this study, a detailed steady state analysis of the new converter is presented, and this theoretical analysis is verified exactly by a prototype of a 1-kW and 100-kHz boost converter.