由FFT芯片构成的并行FFT结构

快速傅立叶变换（ＦＦＴ）在计算机层析影象技术,语间识别,图像处理等域得了广泛的应用。随着计算机应用的发展,越来越需要对大规模的数据进行变换。并行ＦＦＴ是完成快速数据变换的一种方法。本文提出一咱由小规模ＦＦＴ芯片构成并行ＦＦＴ的方法,楞用于大规模数据的变换,并对其并行结构的面积和执行时间进行了探讨,还提出了具有容错功能的并行ＦＦＴ网络。     

A computer-based-design approach to partitioning and mapping of computer logic graphs

A system of design automation computer programs is described which is capable of assigning blocks of a logic design to modules so as to satisfy certain constraints specified on the assignment. System features which enable designer-computer cooperation are discussed, and quality of solutions obtained with the system are compared to manual solutions for the same tasks. Three conclusions are reached. First, these computer programs make it possible to perform partitioning and mapping experiments which were not possible before. Second, for one-level partitions (e.g., logic gates on chips), highly automatic solutions obtained by the system are at least as good as manual solutions and are less costly to obtain. Third, for multilevel partitions (e.g., logic gates on chips on cards) or for mappings, the solutions obtained with the program are again at least as good as manual solutions; furthermore, the system allows a designer to try more alternatives than he could manually, so that he can trade off the time and cost of trying additional alternatives against the value of a better solution.     

大气恒流采样系统的设计与实现

介绍在新型环境检测仪器 β射线空气质量PM10 自动监测仪中 ,如何利用质量流量控制器实现对大气的恒流采样 ,并着重阐述了如何利用AT89C5 5为核心的单片机结合外围数模 /模数转换芯片 ,从电路和软件上实现这一功能的具体应用方法。     

Supercomputers-beyond today's supercomputers

Advanced technologies and their potential for the next generation of supercomputers are addressed. Among them are bacteria serving as lithographic masks, computer chips grown from organic molecules, beams of light in free space acting as input/output `buses', and architectures without logic gates that yield an answer without calculations. The need for a universal computational model for parallel processing is discussed. The use of neural networks is considered     

一种高阶QAM解调系统的硬件平台

为了满足多媒体和计算机通信的需要，以欧洲DVB—C为标准，对正交幅度调制（Quadrature Amplitude Modulation，QAM）信号基本解调原理进行了讨论。重点介绍了一种高阶QAM的硬件解调平台，该系统提高了宽带利用率，可针对不同速率、不同阶数的QAM符号，以专用芯片为基本功能单元，完成时域恢复和载波同步，达到符号收敛，实现各种QAM数字信号的解调。     

The future is in the PC cards

The growing use of IC memory cards, with their small size and low power consumption, in key roles in all sorts of handheld equipment is discussed. Three events that have propelled the credit-card-sized descendants of the original battery-packed memory cards are discussed. They are the development of a standard for 68-pin personal computer cards, known as PC cards, that allows them to act as peripherals, such as modems and network ports, as well as storage devices; the development of flash-type nonvolatile memory chips of very high capacity; and the emergence of palmtop and notebook computers     

Gigabit age microelectronics and their manufacture

The benefits of gigabit chips, which will enter production around the year 2000, are discussed. These chips will be enablers for smart and brilliant systems. The systems will be ultralow power. The design and software productivity enhancements needed are described. The numerous manufacturing challenges that lie ahead in the 1990s represent opportunities to implement advanced concepts currently under development in the industry. It is predicted that software-driven concepts such as flexible manufacturing and distributed computer integrated manufacturing will evolve. Processing concepts using cluster tools, real-time process control, all-dry processing, and wafer microenvironments should be ready for manufacturing in the gigabit age. The costs of electronics should continue to decrease, concomitant with extraordinary increases in functionality and performance     

DSP6416的主机接口(HPI)与USB接口的连接与设计

本文以基于3G技术的移动自组织网(MANET)的研究为背景,用现在较为流行的高速USB接口与DSP的主机接口HPI相连接,成功地解决了MANET移动终端与主机之间的数据交换问题。本文在介绍了TI公司DSP芯片TMS320C6416和CYPRESS公司的USB接口控制芯片CY7C68013特点以后,介绍了两者连接的一种硬件设计以及USB芯片的固件的编写和调试。     

Memory systems for highly parallel computers

Some recent developments in computer memories are discussed, and proposals are made to enhance the memory systems of highly parallel SIMD (single instruction multiple data) computers. The topics covered include increases in density and speed; adding new logic functions to memory chips; local autonomy in addressing; a parallel indexed RAM (PIRAM); impact of memory on numerical computation in SIMD; routing data among processing elements (PEs); bottlenecks; iconic and symbolic processing; a mesh-interfacing memory chip; bimodal memory system; and local address autonomy using PIRAMs     

A 4-bit Josephson computer ETL-JC1

The first computer operation of a 4-b Josephson computer, ETL-JC1 (Electrotechnical Laboratory-Josephson Computer no.1), designed using a reduced instruction set computer (RISC) architecture is described. In the experiment, the computer functions have been verified by executing a computer program installed in a Josephson read-only memory (ROM) at a low repetition frequency. To construct the computer, four Josephson LSI chips including a register and arithmetic logic unit, a sequence control unit, an instruction 1280-b ROM unit, and a 1-kb RAM unit were connected on a nonmagnetic printed circuit board. The Josephson LSI chips were fabricated using Nb/AlO_x/Nb tunnel junctions with 3-μm design rules. The total power dissipation was 6.2 mW in the total circuit, which consists of 22000 junctions including regulators on every chip. On the basis of measurements of the delay times of the logic gates and the access times of the memory chips, it is expected that the program execution in the critical path can be carried out with a single central processing unit in less than 1 ns, resulting in 1 giga-instructions per second (GIPS)     

基于USB-HOST技术的无纸记录仪设计

设计了采用USB-HOST技术、具有大容量FLASH存储器的彩色液晶无纸记录仪,重点讨论基于单片机的USB主机系统的设计方法,给出了Philips ISP1161A芯片与INTEL 80C196单片机的连接电路、USB驱动程序设计方法和程序设计框图.     

VLSI implementation of two-dimensional digital filters via two-dimensional filter chips

The realization of an arbitrary two-dimensional (2-D) rational transfer function which represents an infinite impulse response (IIR) 2-D filter in terms of low-order 2-D polynomials is discussed. These low-order polynomials are implemented via a bit-sliced chip, and are used as standard building blocks for the implementation of the general 2-D digital filter. Different general realization methods are considered and are modified in order to incorporate the standard 2-D chips. The resulting structures have reduced complexity and they exhibit a high degree of regularity and modularity. Furthermore, the number of 2-D low-order filter chips required for the implementation of the given filter is substantially reduced, compared to the number of 1-D chips required by regular general implementations.     

Software-implemented EDAC protection against SEUs

In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment     

Multichip modules: next-generation packages

Multichip modules (MCMs), which interconnect multiple bare dice by means of a stack of conductive and dielectric thin films, are discussed. Among their advantages are reduced delays between chips, simplified power distribution, and enhanced dissipation capabilities. Key design demands that should be weighed by IC design engineers planning to use MCMs are examined. They concern transmission delays, power distribution, heat dissipation, and temperature, as well as testing, burn-in, and rework. The various approaches to MCM packages are described. Factory-programmable versus user-programmable options are considered. Techniques for connecting chips to substrates are discussed     

An analog neural computer with modular architecture for real-timedynamic computations

A multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable is described. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2-μm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications was tested successfully. Results of a network for real-time decomposition of acoustical patterns are discussed     

多模移动终端芯片设计

文章分析了B3G技术可能的演进进程,在此基础上,对移动终端基带处理芯片进行了介绍,并探讨了多模移动终端基带处理芯片的关键技术.文章认为B3G终端技术是B3G技术研究的重点,而移动终端基带处理芯片研发是B3G终端技术研究的重点,为此提出了一种统一无线平台,利用该平台可方便地进行多模移动终端基带处理芯片的研发.     

显卡芯片显示异常的失效分析

显卡芯片是构成计算机最重要的部件之一,运用芯片失效分析的方法和依照严谨的失效分析流程准确迅速地发现芯片失效的根本原因对显卡芯片及计算机系统集成制造的品质改善至关重要。由于显卡芯片具有一定的特殊性,因此我们根据半导体器件失效分析的基本流程提出了针对显卡芯片显示异常的失效分析的改进流程。同时通过对一组显卡芯片显示异常实际案...     

Digital signal processing

Markets have always influenced the central thrust of the semiconductor industry. Beginning in the early eighties, the personal computer (PC) market has been the dominant market influencing the semiconductor industry. Single-chip microprocessors (MPUs) enabled what became the huge PC market, which ultimately overshadowed the earlier minicomputer and mainframe computer markets. The popularity of PCs led to investments in increasingly more powerful MPUs and memory chips of ever-growing capacity. MPUs and DRAMs became the semiconductor industry technology drivers for the data processing needs of the PC. But now, DSP, as opposed to conventional data processing, has become the major technology driver for the semiconductor industry as evidenced by its market growth and the fervour of chip vendors to provide new products based on DSP technology. The increasing need to digitally process analog information signals, like audio and video, is causing a major shift in the semiconductor business. Since DSP is the mathematical manipulation of those digitized information signals, specialized math circuitry is required for efficient signal processing-circuitry that was previously confined to classical DSP chips     

具有激光二极管结构的1.3μm侧面发光二极管（Ⅰ）：理论分析

讨论了用某些参数不合格的激光二有管管芯制作侧面发光二极管的可能性，并给出了超辐射发光二极管和侧面发光二极管的定量判定依据。     

Embedding spectral analysis in equipment

The use of digital signal processors (DSPs) that enable continuous estimates of signal frequency components to be incorporated into a broad range of real-time systems is considered. Classical spectral estimation methods are reviewed. Real-time implementation of the methods, all of which use some form of fast Fourier transform method, on DSP chips is discussed. Some applications of these chips are examined