Modeling and analysis of power extraction circuits for passive UHF RFID applications

Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear ap-proximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.     

应用于无源超高频射频识别卡芯片的能量提取电路建模与分析

Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.     

太赫兹倍频器研究进展

太赫兹CMOS电路具有小型化、与大规模硅基工艺兼容的特点,非常适合未来太赫兹通信以及5G通信的应用。本文以太赫兹CMOS本振电路为切入点,调研了国际和国内的最新CMOS倍频器电路结构,在此基础上,对推推(push-push)倍频器、注入锁定倍频器以及混频倍频器的电路结构和特点进行了详细介绍。通过对以上几种倍频器的分析对比,总结了不同的倍频器在实际应用中的优缺点,为太赫兹射频前端小型化实际应用奠定基础。     

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.     

Switched-opamp: an approach to realize full CMOS switched-capacitorcircuits at very low power supply voltages

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-μm CMOS process with V_T=±0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV_ptp and a powerdrain of only 110 μW     

Ultra-area-efficient reversible multiplier

One of the most promising technologies in designing low-power circuits is reversible computing. It is used in nanotechnology, quantum computing, quantum dot cellular automata (QCA), DNA computing, optical computing and in CMOS low-power designs. Because of this broad range of applications, extensive works have been proposed in constructing reversible gates and reversible circuits, including basic universal logic gates, adders and multipliers.In this paper we have highlighted the design of reversible multipliers and have presented two designs. Integration of adder circuit and multiplier in the design is described, in order to utilize the unused capacity of the multipliers.We have achieved reduction in quantum cost compared to similar designs as well as appending the adder circuit to the multiplier which leads to better usage of resources. Additionally, we have described the multiplier problem for implementing n×n reversible multiplier and analyzed the required resources in terms of n. Practical implementation of this design can be achieved with the existing technologies in CMOS and nanotechnology.Lastly, we make a tradeoff between area and time complexity to obtain two designs which can be used in different situations where different requirements are of different importances. We compare the proposed designs with each other and also to the existing ones.     

超高频无源RFID标签的一些关键电路的设计

本文针对超高频无源RFID标签芯片的设计,给出了一些关键电路的设计考虑。文章从UHFRFID标签的基本组成结构入手,先介绍了四种电源恢复电路结构,以及在标准CMOS工艺下制作肖特基二极管来组成倍压电路的解决方案。然后针对电源稳压电路,提出了串联型和并联型两种稳压电路。文章针对ASK包络解调电路,提出了新的泄流源的设计。最后,文章介绍了启动信号产生电路的设计考虑。     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V_dd², decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.     

An 8.8-ns 54×54-bit multiplier with high speed redundantbinary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54×54-bit multiplier is designed with this architecture. It is fabricated by 0.5 μm CMOS with triple level metal technology. The active area size is 3.0×3.08 mm² and the number of transistors is 78,800. This is the smallest number for all 54×54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54×54-bit multipliers with 0.5-μm CMOS     

基于忆阻器的乘法器电路设计

忆阻器作为一种非易失性的新型电路元件,在数字逻辑电路中具有良好的应用前景。目前,基于忆阻器的逻辑电路主要涉及全加器、乘法器以及异或(XOR)和同或(XNOR)门等研究,其中对于忆阻乘法器的研究仍比较少。该文采用两种不同方式来设计基于忆阻器的2位二进制乘法器电路。一种是利用改进的“异或”及“与”多功能逻辑模块,设计了一个2位二进制乘法器电路,另一种是结合新型的比例逻辑,即由一个忆阻器和一个NMOS管构成的单元门电路设计了一个2位二进制乘法器。对于所设计的两种乘法器进行了比较,并通过LTSPICS仿真进行验证。该文所设计的乘法器仅使用了2个N型金属-氧化物-半导体(NMOS)以及18个忆阻器(另一种为6个NMOS和28个忆阻器),相比于过去的忆阻乘法器,减少了大量晶体管的使用。     

基于标准CMOS工艺的UHF无源通讯电源电路设计与实现

针对UHF射频无源通信系统中,无源射频接收端的电源电路设计难题,以提高其电源转换电路的能量转换效率和输出电压的稳定性为目标,研究了在标准CMOS工艺下实现肖特基二极管的方法,并从理论上推导了其传输特性,提出了一种新型的限压电路,改进了传统带隙结构。与传统结构相比,新的UHF射频无源通信接收端的电源电路的能量转换效率高,开启速度快,输出电压稳定性更好,能够大幅改善射频无源接收电路的工作性能。最后还给出了芯片实现的版图,以及模拟和测试结果。     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

带新解调结构的UHF RFID标签低功耗模拟前端设计

基于ISO/IEC 18000-6C协议,对UHF无源电子标签模拟前端中的ASK解调电路、整流器、稳压电路等进行低功耗设计。解调电路中微分电路的加入扩大了解调电路工作范围,在解调电路近距离工作时,可以更有效地解调。整流电路采用了零阈值MOS管代替肖特基二极管,降低芯片成本。整流稳压电路可稳定地为芯片供电,供电电压2 V,建立时间仅为25μs。电路采用SMIC 0.18μm 2P4M CMOS工艺进行流片,芯片面积720μm×390μm。测试得到模拟前端整体工作电流仅2.4μA,标签工作距离大于7 m。     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders

This paper presents a RF to DC conversion model for multi-stage rectifiers in UHF RFID transponders. An equation relating the RF power available from the antenna to the DC output voltage produced by a multi-stage rectifier is presented. The proposed model includes effects of the nonlinear forward voltage drop in diodes and impedance matching conditions of the antenna to rectifier interface. Fundamental frequency impedance approximation is used to analyze the resistance of rectifying diodes; parasitic resistive loss components are also included in the analysis of rectifier input resistance. The closed form equation shows insights into design parameter tradeoffs, such as power available from the antenna, antenna radiation resistance, the number of diodes, DC load current, parasitic resistive loss components, diode and capacitor sizes, and frequency of operation. Therefore, it enables the optimization of rectifier parameters for impedance matching with a low-cost printed antenna and shunt tuning inductor, in order to improve the RF to DC conversion efficiency and the operational distance of UHF RFID transponders. Three diode doublers and three multistage rectifiers were fabricated in a 130 nm CMOS process with custom no-mask added Schottky diodes. Measurements of the test IC are in good agreement with the proposed model.      

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP™) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.      

A CMOS transconductance amplifier architecture with wide tuningrange for very low frequency applications

A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small G_M's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown