An integrated single-chip PCM voice codec with filters

A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

An on-chip smart memory for a data-flow CPU

Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional read and write operations. An experimental 1240-b smart memory chip is implemented in a 1.6-μm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34658 transistors, occupies an area of 3.8 mm×5.2 mm, and dissipates 0.51 W     

基于多核CPU和GPU的高光谱数据并行几何校正

针对高光谱几何校正计算复杂,大数据量频繁传输降低处理效率,无法满足实时需求等问题,提出基于多核CPU和GPU的并行计算模型。实现基于GPU的并行几何校正,并引入流水线并行思想提出基于多线程的数据读写优化方法,实现重采样部分的数据I/O优化。应用航空推扫成像仪所得高光谱数据进行实验,验证该方法能够有效地隐藏部分硬盘与内存间的数据I/O时间,几何校正加速比达到4.03,在基于GPU的并行计算基础上提高了1.74倍。     

基于AT89S52单片机数据通信终端设计

目前,以单片机为核心的应用技术越来越广。文中基于AT89S52单片机控制技术,设计了一个数据通信终端,对其系统的原理、构成和技术特点进行介绍。达到可以实时、稳定传输数据的预期,在无线遥控方面有一定的应用。     

Synchronous data flow

Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.     

CPU常见病

病例：开机后本来166MHz的CPU变成133MHz了，显示的信息是“Defaults CMOS Setup Loaded”，在重设置CMOS Setup中CPU参数后（软跳主板），系统正常显示166MHz主频，但不知何时，又会重复上面的过程。这种现象常见于软设置CPU参数的主板。普通的钮扣型锂电池是3V的，实际测量应     

Experimental single-chip PABX

Experimental VLSI techniques and an architectural concept are described which permit the realization of an experimental single-chip private automatic branch exchange (PABX) for switching voice and data. Analysis indicates that up to 40 telephones and 40 data terminals could be interconnected with a single chip. The architecture makes it possible to interconnect multiple PABX chips to form a larger system. The single-chip concept is made possible by distributed switching near the subscriber, digital interface, a new `orthogonal' RAM, and a low-power line-driving technique, all of which are included in this investigation.     

软件CPU

在当今的电脑世界中，英特尔公司是制造微处理器的霸主，多少年来一直没有人能与之匹敌。然而前不久，人们听到了一个消息，一个名不见经传的小公司突然发布了一款“软件ＣＰＵ”，不仅要与微软抗衡，还想跟英特尔叫板。一个小公司居然借助互联网的魔力把自己设计的ＣＰＵ拿出来挑战英特尔，着实让大家都吃了一惊。当然这个小公司不会自己投资生产线去生产这些产品，他们只管设计处理器，生产可以由其他大公司来完成。到底谁会支持他们，目前还是一个谜。但是可以肯定，英特尔决不会支持。《微处理器》杂志的一位分析家说，这个产品必定让英…     

CPU展望

当与PC微处理器供应商AMD公司和Intel公司谈论即将来临的GPU(图形处理设备)竞争威胁时,得到的回答是不相同的.AMD公司微处理器业务部门负责服务器与工作站业务的产品经理SteveDemski在2005年7月初于洛杉矶召开的Siggraph研讨会上说:"我在有TCP/IP卸载硬件的服务器上看到了同样的事情.我认为这是件好事.只要GPU可以做得更好、更快、更便宜,当然是件好事.这样能够让通用CPU腾出手来做更多的其他工作."     

Beyond transborder data flow

The unique nature of information gives rise to troublesome questions regarding traditional economic theory, ownership rights and the role of the government. Today, one of the main focusses of international information policy concerns the flow of data across national boundaries. One finds a disappointing outline of a new spirit of “double standards” in the U.S. information policy. The earlier spirit calling for unrestricted flow of information across international boundaries is being replaced by a form of “America first” philosophy.     

基于虚拟仪器和PIC单片机的USB接口数据采集系统设计

围绕虚拟仪器技术数据传输接口的研究,结合PIC18F258单片机,开发了具有即插即用功能的USB接口数据采集系统,包括CAN总线控制模块、D/A转换模块和温度采集模块。并给出了利用虚拟仪器开发环境LabVIEW实现上位机监控面板的设计过程。实践表明,该虚拟仪器数据采集系统使用灵活,为工业现场数据采集与处理提供了方便。     

An amoeboid approach for identifying optimal citation flow in big scholarly data network

Scholarly big data network is a complex network of citations from research community across the globe. An effective scholar assessment structure is essential for scholars, researchers, and universities. The research publications are an important factor in the university rankings. The fast growth of digital publishing and scholarly data is progressively challenging every day. These days, the scholarly data can be accessed effortlessly through various data analysis techniques. In this paper, a new framework is designed for big scholarly data, and an amoeboid approach article‐optimal citation flow (A‐OCF) is used to find the optimal flow of citations in the big scholarly data network. A novel modern metrics for article quality (MMAQ) metric is proposed to identify the quality of articles. The performance analysis uses different bibliometric measures, including the impact factor citations, conference proceedings citations, and other citations with the purpose of measuring the quality of cited articles. The scholar analytic results are equated with existing techniques. We have also analyzed central articles in a research area through the MMAQ metrics and tested it with benchmark data sets.     

CPU新技木

处理器市场上AMD与Intel这对冤家的竞争总是没完没了,两家轮流坐庄,抢先发布产品.一时的领先并不代表永远的胜利,CPU战场上总会有令人惊讶的事情发生.Crusoe处理器构架曾让Intel与AMD伤透了脑筋,因为已有厂商用这种另类处理器构架做出了相当于Pentium Ⅲ等级的CPU.这种低成本CPU极有实力与大厂抢夺低价处理器市场,看来即使Intel、AMD不伤脑筋,后起之秀VIA也要开始担心了.     

获取CPU信息

很多软件可以判断所运行的电脑类型而自动做不同的处理。如PhotoShop 5可以探测CPU是否有MMX支持而调用不同的处理函数，《金山词霸》发现有MMX支持会产生半透明的翻译提示，很多软件可以区分Intel，Cyrix，AMD的CPU……以下介绍如何让你在自己的程序中取得CPU信息。主要可利用     

CPU大观

CPU 是电脑的心脏，也是电脑发展的一个最重要的标志，我们所说的电脑的档次实际上就是按照电脑中所安装的CPU 的档次而决定的。现在，CPU 的技术和市场已经开始慢慢地发生着变化，Intel 以前独霸市场的景象正在改变，AMD、VIA 等厂家的迅速崛起，正引导我们走入一个五彩缤纷的CPU 世界，Intel 一方独好的局面实际上对于我们来讲并不是太好的事情。下面，让我们一起来回顾一下CPU 的厂家、产品，同时展望一下不远的将来。IntelPent i um就是大名鼎鼎的“奔腾”处理器，它是Intel 在1993年推出的全新一代的高性能处理器，内部代号…     

一种基于P87LPC769CPU控制的自动引导车

文章介绍了一种两轮驱动的自动引导车 ,其主控单元为P87LPC76 9单片机。通过一闭环系统对自动引导车直线、转弯行驶进行实时控制。     

An nMOS VLSI process for fabrication of a 32-bit CPU chip

An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology utilizes 1.5-/spl mu/m lines and 1.0-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization. The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow. Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology.     

A single-chip tuner for DVB-T

A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.