CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.     

A CMOS Analog Cell and its applications in analog signal processing

This paper presents a core cell that can be reconfigured and combined with current mirrors to implement exponential, logarithmic, multiplier, divider and raise-to-power function circuits. The proposed circuit uses CMOS transistors operating in the strong inversion. The proposed circuits has been verified with the 0.8?µm CMOS technology by HSPICE simulations. The simulations results confirm the functionality of the proposed circuits. The proposed circuits paves the way for designing analog signal processors.     

集成CMOS四象限模拟乘法器

给出了一种CMOS型四象限模拟乘法器，该乘法器采用有源衰减器结合吉尔伯特单元结构.利用基于CSMC的0.6μm n阱2p2m工艺SPICE BSIM3V3 MOS模型(level=49)进行仿真，采用单电源5V电压供电.利用HSPICE仿真并给出了仿真的结果及版图实现.     

Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation.     

高精度单向模拟开关的设计及其基于CMOS工艺的电路实现

提出并设计了一种基于 CMOS工艺实现的高速高精度的单向隔离模拟开关 ,该开关用在高速两步法 A/D转换器中使电路结构大为简化 .通过对开关特性的理论分析与电路模拟 ,证明了这种模拟开关具有高速可控性 ,传输信号的精度优于先前研究的双极单向隔离模拟开关     

一种低压高线性CMOS模拟乘法器设计

提出了一种新颖的CMOS四象限模拟乘法器电路．该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0．18μmCMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1．8V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0．3V,-3dB带宽可达到1GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。     

A High Speed, Low Voltage CMOS Offset Comparator

A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0–3.6 V and 1.6–2.0 V supplies and –40 to 125°C temperature range on a typical 0.5 m technology.     

A Current Mirror for Low Voltage, High Performance Analog Circuits

A current mirror for low voltage analog and mixed mode circuits is proposed. The current mirror has high input and output voltage swing capability and can operate at ±1.0 V supply. P-Spice simulations confirm the input current range of 1 A to 500 A with 2.5 GHz bandwidth for the proposed current mirror. Adaptive biasing increases the input voltage swing capability and decreases the undesired offset current. Resistive and capacitive compensation are used to increase its bandwidth.     

CMOS数字集成电路的高温电学性能分析

本文给出了ＣＭＯＳ倒相器的高温等效电路，分析了它的高温直流传输特性和瞬态特性，文章还讨论了ＣＭＯＳ静态数字集成电路高温电学特性的分析方法。本文提出了的ＣＭＯＳ数字集成电路的高温学特性模型和实验结果相接近。     

A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V_p-p input signal at 2.5 V supply voltage, and that the 3 dB bandwidth is up to about 13.3 MHz.     

一种结构简单的低压CMOS四象限模拟乘法器

提出了一种结构简单、采用有源衰减器的低压ＣＭＯＳ四象限模拟乘法器。详细分析了电路的结构和设计原理,给出了电路的ＰＳＰＩＣＥ模拟结果。模拟结果表明,当电源电压为±１．５Ｖ时,功耗小于８０μＷ,线性输入电压范围约为±０．５Ｖ;当输入电压范围限于±０．３Ｖ时,非线性误差小于１．３％;－３ｄＢ带宽约为３．２ＭＨｚ。该乘法器电路可应用于低压模拟信号处理电路中。     

CMOS亚阈值特性的低频低压微功耗电路的设计与模拟

工作在亚阈值状态的MOS晶体管具有极小的工作电流和类似于双极型晶体管的指数特性,因此适合于实现微功耗的外部线性内部非线性电流型电路.为了适合于低电源电压的运用,本文给出了一种新型的电流型四象限乘法器以及滤波器,振荡器等基本单元电路,并利用标准0.6-μm CMOS的工艺参数以锁相环为例进行了性能模拟验证.     

A Gigabit Link CMOS Analog Interface for High Performance Signaling

In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 μm CMOS process. Sungkyung Park Large Scale SoC Research Department, Electronics and Telecommunications Research Institute(ETRI), 161 Gajeong-dong, Yuseong-gu, Daejeon 305–350, Korea (fitzgerald1971@yahoo.com) Sungkyung Park received B.S. (with highest honors) and M.S. degrees from Seoul National University, Korea, in 1995 and 1997, respectively. He received a Ph.D. degree in CMOS IC design from Seoul National University, Korea, in 2002. During the military service, from 2002 to Sep. 2004, he was with the Telecommunication Network, Samsung Electronics, Inc., Korea, as a Senior Engineer, where he was engaged in developing cdma 2000 system-level simulators. From Oct. 2004 until now, he has been with the Large Scale SoC Research Department, Electronics and Telecommunications Research Institute (ETRI), Korea, as a Senior Researcher. His research interests cover high-speed analog and mixed-mode CMOS IC design including RF CMOS IC design, data converter design, and issues in wireless/wireline communication SoC/NoC.     

Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V _t |+2 V _ds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 m N-well process with a 3 V supply are given.     

High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

This paper describes a CMOS building block dedicated to high performance mixed analog-digital circuits and systems. The circuit consists of six MOS transistors realizing a new wideband and tunable transconductance. The theory of operation of this device is presented and the effects of transistor nonidealities on the global performances are investigated. Use of the proposed circuit to realize tunable functions (Gm-C filter and current opamp) is illustrated. HSPICE simulations show a wide tuning range of the transconductance value from 40 S to 950 S (500 S) for ±2.5 V (±1.5 V) supply voltages. The transconductance value remains constant up to frequencies beyond 500 MHz. The bandpass filter built with few transconductance blocks and capacitances was simulated with ±2.5 V supply voltage, the center frequency is tunable in the range of 30 MHz to 110 MHz. However, the opamp, which is designed with a transresistance-transconductance architecture, was simulated with ±1.5 V supply voltage. The gain of the opamp can be tuned between 70 dB and 96 dB and high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW. Experimental results on a fabricated transconductor chip are provided.     

CMOS四路可加权高频模拟开关的设计和研究

介绍了一种可对高频信号进行取样、加权、控制、叠加的模拟信号处理开关集成电路,通过两个高宽长比的高跨导NM O S晶体管可实现权值的粗调和微调。该电路采用标准0.6μm CM O S工艺制造。测试结果表明:该电路的工作频段为50~250 MH z时,导通时最小插入损耗约为-5.0~-10.5 dB,关断时隔离度可达-40.5~-23.4 dB左右;其连续可调的加权动态范围最大值为21.3 dB。     

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-m CMOS technology validate on silicon the proposed technique.     

一种宽输入范围CMOS模拟乘法器的优化设计

设计了一种基于CMOS工艺设计的宽输入范围的Gilbert单元乘法器.通过在乘法器的输入端加入有源衰减器和电位平移电路,增大了乘法器的输入范围(±4 V).该乘法器采用TSMC 0.35 μm的CMOS工艺进行设计,并用HSpice仿真器对电路进行了仿真,得到了电源电压为±4 V,以及线性电压输入范围为±4 V时,非线性误差小于1.0%,乘法运算误差小于0.3%,x输入端的-3 dB带宽为470 MHz,y输入端的-3 dB带宽为4.20 GHz的良好结果,整个乘法器电路的功耗为2.82 mW.