Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

On the dynamic NBTI of the HfO2 and HfSiON P-MOSFET

Under typical dynamic NBTI conditions (∼7 MV/cm, 100 °C), a progressive decrease in the recoverable component (R) of the HfO₂ p-MOSFET is observed but those of the HfSiON and SiON p-MOSFETs are found to remain constant. The decrease in the R of the HfO₂ p-MOSFET is shown to be a result of its conversion into a permanent form. Under a given oxide field and temperature, the R of the HfO₂ p-MOSFET is found to exhibit the greatest tendency to be converted into a permanent form. This behavior is shown to be related to the evolution of hole traps in the HfO₂ and could be explained in terms of the generally more ionic character of high-κ dielectrics.     

Characterization of transient currents in HfO2 capacitors in the short timescale

We present a detailed experimental investigation of transient currents in HfO₂ capacitors in the short timescale. We show that the transient currents flowing through the capacitor plates when the gate voltage is reset to zero after a low voltage stress period follow a power-law time dependence t^−α (with α ? 1) over more than eight decades of time and down to the μs timescale. As transient currents in HfO₂ are largely increased with respect to the SiO₂ case, these results confirm that transient effects can be a severe issue for the successful integration of high-k dielectrics.     

High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy

Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd₂O₃ prepared by molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO₂ prepared by reactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.     

Reliability of charge trapping memories with high-k control dielectrics (Invited Paper)

In this paper, we evaluate the potentiality of high-k materials (Al₂O₃, HfO₂ and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO₂/Si₃N₄/SiO₂/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention.     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Ge volatilization products in high-k gate dielectrics

GeO molecules are often emitted by Ge substrates under high-temperature annealing and, in the case of gate stacks, they diffuse through high-k oxides. Here we use first-principles quantum-mechanical calculations to probe the stability of these impurities in La₂O₃ and HfO₂ and their effect on the electronic properties of the host systems. We find that the GeO species introduce several different levels inside the energy band gaps of La₂O₃ and HfO₂. As a result, the impurities may act as charge carrier traps. Hydrogenation of the GeO defects modifies the position and numbers of gap states, but does not eliminate the carrier trap levels completely. The results suggest a possible role of Ge volatilization in enhancing leakage currents and degradation in high-k gate stacks of Ge-based devices.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

BOOK REVIEWS

Book reviewed in this articles:
U nobtrusive M easures : N onreactive R esearch in the S ocial S ciences . By Eugene J. Webb, Donald T, Campbell, Richard D. Schwartz, and Lee Sechrest
M athematics and P sychology . By George A. Miller
I nterpersonal D ynamics : E ssays and R eadings on H uman I nteraction . By Warren G. Bennis, Edgar H. Schein, and David E. Berlew
R oles : A n I ntroduction to the S tudy of S ocial R elations . By Michael Banton.
T he C reative O rganization . Edited by Gary Sterner
A rgumentation and D ebate : R ational D ecision M aking . By Austin J. Freeley
A dvertising the L ocal C hurch . By James W. Carty, Jr.
P hilosophy , R hetoric, and argumentation . Edited by Maurice Natanson and Henry W. Johnstone, Jr.
R hetoric —A P hilosophical I nquiry . By A. Craig Baird.
B riefly N oted
T he T ruman P residency : T he H istory of a T riumphant S uccession . By Cabell Phillips.
L anguage and P olitics . Edited by Thomas O. Brockway
F reedom of the P ress in E ngland : 1476–1776. By Frederick Seaton Siebert
S peech P reparation S ourcebook . By Robert T. Oliver, Carroll C. Arnold, and Eugene E. White
B usiness C ommunications for B etter H uman R elations . By Charles Chandler Parkhurst
T he P ractice of C riticism . By Sheldon P. Zitner, James D. Kissane, and M. M. Liberman
T each W ith T elevision : A G uide to I nstructional TV. By Lawrence F. Costello and George N, Gordon.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

TCAD leakage current analysis of a 45 nm MOSFET structure with a high-<Emphasis Type="Italic">k</Emphasis> dielectric

The models of electrophysical effects builtinto Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFETs with polysilicon gate and SiO₂, SiO₂/HfO₂ and HfO₂ gate dielectrics have been calculated using TCAD. It has been shown that the replacement of the traditional SiO₂ gate oxide by an equivalent HfO₂ dielectric reduces the gate leakage current by several orders of magnitude due to the elimination of the impact of the tunneling effect. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc., degrade within a range of 10–20%.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

在metal/high-k 栅叠层中插入Ti/TiN金属层实现远距离吸氧技术

High permittivity materials have been required to replace traditional SiO₂ as the gate dielectric to extend Moore’s law.However,growth of a thin SiO₂-like interfacial layer（IL） is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO₂ dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO₂ have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.     

Initial leakage current related to extrinsic breakdown in HfO2/Al2O3 nanolaminate ALD dielectrics

Multiple successive breakdown events are reported for HfO₂/Al₂O₃ nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiO_x layer at the silicon substrate/dielectric interface.