Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects

The crosstalk effects in single- and double-walled carbon-nanotube (SWCNT and DWCNT) bundle-interconnect architectures are investigated in this paper. Some modified equivalent-circuit models are proposed for both SWCNT and DWCNT bundles, where capacitive couplings between adjacent bundles are incorporated. These circuit models are further used to predict the performance of SWCNT and DWCNT bundle interconnects in comparison with the Cu wire counterpart at all interconnect levels for advanced future technology generations. It is found that, compared with the SWCNT bundle, the DWCNT bundle interconnect can lead to a reduction of crosstalk-induced time delay, which will be more significant with increasing bundle length, while the peak voltage of the crosstalk-induced glitch in SWCNT and DWCNT bundle interconnects is in the same order as that of Cu wires. Due to the improvement in time delay, it is numerically confirmed that the DWCNT bundle interconnect will be more suitable for the next generation of interconnect technology as compared with the SWCNT bundle counterpart.      

一种有效的变线宽时钟布线算法

针对时钟布线提出了一种有效的变线宽算法。该算法通过对时钟树中各树枝延迟敏感度的分析,选择总体最优的连线进行变线宽处理,使得时钟树的路径延迟最小化。在延迟优化后,为了使时钟偏差小于给定的约束,通过变线宽对各种钟汇点的延迟进行全面的再分配,使延迟最大的时钟汇点延迟最小化,而延迟较小的路径延迟适当增加,以进一步改善时钟树延迟。实验结果表明,该算法有较高的运行效率,时钟树的路径路径和时钟偏差得到了显著的改     

Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect

In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of wire inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of the transistors are optimized to accelerate the signal propagation while consuming minimum power. In 90-nm CMOS technology, STR design achieved a delay improvement of 14% over the conventional repeater design. Furthermore, 20% power reduction is achieved for iso-delay, and 8% delay improvement for iso-power compared with the repeater design. The proposed technique has also been applied to a clock distribution network, reducing clock power by 26%.     

Optimal bus sizing in migration of processor design

The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimally-tuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sum-of-delays problem. An iterative algorithm to find the optimally-tuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

The future of wires

Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-μm to 0.035-μm feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these “local” wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms     

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

VLSI interconnect issues in definitive and stochastic environments

A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast estimation. The average and maximum error of this look-up-table is less than 1% and 7.7% respectively, compared to HSPICE results. Second, the statistical environment of a wire in a BUS configuration is studied for all possible different switching patterns happening for the wires. Estimating the BUS main problems, including power consumption, crosstalk, and propagation delay for a random environment, which a wire senses in wide BUS, is only possible with statistical parameters like mean and variance. All simulations are done considering both wire inductive and capacitive couplings in HSPICE. Also, the secondary effect of crosstalk on propagation delay and power consumption is considered. The simulation results show 3.81% of BUS input switching can lead to a wrong decision on its wire load due to the crosstalk induced voltages in 90 nm technology. The average induced crosstalk aware power consumption is 94 μW. Also, the average of maximum crosstalk on the load can be as high as 25% of the V_dd.     

铜与金引线的特性比较

近来由于黄金价格的强势增长,使得作为低成本键合引线的的铜丝受到众多封装界内的关注。如一些粗引线的低引脚封装,业已用铜引线在批量生产中获得成功。当采用这种引线时,它需要一些与金引线不同的条件,例如氧化的程度,机械特性,键合机操作的应用范围等。因此,当用户开始采用铜引线时,就必须考虑减少试验和误差。如果黄金价格继续走高,向铜引线的转化速度将会加快。     

Contributions to VLSI computational complexity theory from bounds on current density

The grid models of VLSI algorithms embody the common assumption that time delays on wires of length L are O(log L). We show that the hierarchical model of driver circuitry responsible for this result is restricted, in its application to asymptotic complexity determinations, by the physical upper bound on current density in the wires for any VLSI technology. Unlike other alternative models of wire delay concerned with resistive properties of the wires or transmission line effects, there are no practical technological fixes for current density limits. It is suggested that the appropriate model for physically realizable VLSI algorithms should contain asymptotic wire delays that are Q(L).     

Mechanical and electrical characterisation of Au wire interconnects in electronic packages under the combined vibration and thermal testing conditions

This paper concerns the reliability of thermosonically bonded 25 μm Au wires in the combined high temperature with vibration conditions, under which the tests have been carried out on wire-bonded 48-pin Dual-in-Line (DIL) High Temperature Co-fired Ceramic (HTCC) electronic packages. Mechanical, optical and electrical analysis has been undertaken in order to identify the failure mechanisms of bonded wires due to the combined testing. The results indicated a decrease in the electrical resistance after a few hours of testing as a result of the annealing process of the Au wire during testing. In general, ball shear and wire pull strength levels remained high after testing, showing no significant deterioration due to the tests under the combined high temperature and vibration conditions. However, a trend of the variation in the strength values is identified with respect to the combined conditions for all wire-bonded packages, which may be summarised as: (i) increase of the testing temperature has led to a decrease of both the shear and pull strength of the wire bonds; (ii) the mechanical behaviour of the wires is affected due to crystallisation that leads to material softening and consequently the deformation of wire.     

In situ ultrasonic force signals during low-temperature thermosonic copper wire bonding

Ultrasonic in situ force signals from integrated piezo-resistive microsensors were used previously to describe the interfacial stick-slip motion as the most important mechanism in thermosonic Au wire ball bonding to Al pads. The same experimental method is applied here with a hard and a soft Cu wire type. The signals are compared with those obtained from ball bonds with standard Au wire. Prior to carrying out the microsensor measurements, the bonding processes are optimized to obtain consistent bonded ball diameters of 60 μm yielding average shear strengths of at least 110 MPa at a process temperature of 110 °C. The results of the process optimization show that the shear strength c_pk values of Cu ball bonds are almost twice as large as that of the Au ball bonds. The in situ ultrasonic force during Cu ball bonding process is found to be about 30% higher than that measured during the Au ball bonding process. The analysis of the microsensor signal harmonics leads to the conclusion that the stick-slip frictional behavior is significantly less pronounced in the Cu ball bonding process. The bond growth with Cu is approximately 2.5 times faster than with Au. Ball bonds made with the softer Cu wire show higher shear strengths while experiencing about 5% lower ultrasonic force than those made with the harder Cu wire.     

一种0.18 μm特大规模芯片快速收敛的设计方法

在0．18μm下，时序收敛的关键是互连线延时问题。文章介绍了一种时序快速收敛的RTL到GDSII的设计方法，该方法有效地消除了逻辑综合和物理设计之间的迭代。采用一个450万门超大规模DSP芯片设计验证了该方法。实例设计结果表明，这种新的方法不但有效地解决了互连线时延的问题，而且缩短了芯片的设计周期。     

Reliability of thick Al wire: A study of the effects of wire bonding parameters on thermal cycling degradation rate using non-destructive methods

The effect of bonding parameters on the reliability of thick Al wire bond is investigated. Samples were prepared with 25 different designs with 5 different bonding parameters such as time, ultrasonic power, begin-force, end-force and touch-down steps (pre-compression) with 5 levels. The bond signals of ultrasonic generator were collected during bonding in order to obtain prior quality information of bonded wires. 3D X-ray tomography was then used to evaluate bond quality during passive thermal cycling between −55 °C and 125 °C. Tomography datasets were obtained from the as-bonded condition and during cycling. The results clearly show ultrasonic power, appropriate levels of begin-force and touch-down steps are all important for achieving a well attached and reliable bond. Analysis of the virtual cross-sections indicates a good correlation between the bond signal (i.e. the initial bond quality) and wire bond damage/degradation rate. An improved understanding of the wire bonding process was achieved by observing the effect of the complex interaction of bonding parameters on the ultrasonic generator signals and degradation rate under thermal cycling.     

微波控制电路中PIN管的引线互连技术

说明了对微波器件"PIN管"在引线互连方面的特殊要求,即键合两根"交叉线"所获得的微波性能大大优于键合单根引线,达到了低插损、低驻波、高隔离度的指标要求,使微波控制电路的高频性能更加优良;简要介绍了"键合交叉线"工艺技术的改进与优化,并且详细叙述了"交叉线"键合工艺的具体操作方法.     

Wire-bonding process development for low-k materials

A 60-μm bond-pad-pitch wire-bonding process was developed using test dies with a SiO₂ dielectric layer under aluminium pads, and was then fine-tuned for a low-k device using three types of gold wires with different mechanical properties. Bulk material hardness of the wires were characterised using a wire-bonding machine, the force applied and diameters of squashed free-air balls. It was found that stiffer wires needed higher ultrasonic-generator (USG) power than a softer wire to deform the ball after impact and achieve equivalent ball size and ball shear responses. Longer bond time was also needed for the low-k material than the SiO₂ material, to overcome the energy loss due to the compliance of the low-k material. Pad damage on the low-k device was proportional to bulk material hardness. The soft 4N (99.99% purity) wire required lower USG power to achieve the bonding specification, and was the most suitable wire to be used in wire bonding of the low-k device.     

一种非零偏差时钟网布线算法

特定的非零偏差时钟网比零偏差时钟网更具优势,它有助于提高时钟频率、降低偏差的敏感度.文章提出了一种新的非零偏差时钟树布线算法,它结合时钟节点延时和时钟汇点位置,得到一个最大节点延时次序合并策略,使时钟树连线长度变小.实验结果显示,这种算法与典型的最邻近选择合并策略相比较,可以减少20%～30%的总连线长度.     

Design concept for wire-bonding reliability improvement by optimizing position in power devices

The most effective way to increase the reliability of wire bonds in IGBT modules is reduction of temperature difference between the aluminum wires and the device. However, this lowers the power handling capability of the modules. In this paper, we show that the configuration of aluminum wire bonds on power devices has a considerable effect on the temperature distribution of the device, and that the optimization of the layout by thermo-electric simulation can make the temperature distribution of the devices more uniform and consequently reduce the maximum junction temperature difference, ΔT_jmax. Tentative experiments showed that rearranging the bonding position resulted in reduction of ΔT_jmax by five to 8 °C, and that the chip temperature distribution estimated by the thermo-electric simulation was qualitatively similar to the actual measurement results. These results suggest that wire-bonding optimization by thermo-electric simulation can contribute not only to realizing more compact power modules but also to improving the module reliability.     

Comparison of Insulated with Bare Au Bonding Wire: HAZ Length,HAZ Breaking Force,and FAB Deformability

Two types (A and B) of 25-μm-diameter bare Au bonding wire and their corresponding insulated wire were used to produce 50-μm-diameter free-air balls (FABs) for heat-affected zone (HAZ) and FAB deformability analyses. Insulated wires showed no significant difference in HAZ length compared with bare wire for type A, while their difference lay in the range of 4% to 12% longer for type B. The HAZ breaking load of bare wire is 0.3% to 1.8% smaller than that of insulated wire for type A and not significantly different for type B even though the HAZ length is shown to be larger for insulated wire B. The deformability of the FAB from insulated wires is 1.0% to 2.1% smaller than that from bare wires for type A and 2.1% to 3.4% larger for type B.     

Development of capillaries for wire bonding of low-k ultra-fine-pitch devices

Although wire bonding has been a well-established technology for many years, the bonding tool design becomes more complex and the process is very sensitive for wire bonding of low-k ultra-fine-pitch microelectronics devices. In this study, two different types of external transition profile were considered in order to use lower ultrasonic-generator power for preventing pad damage. The ultrasonic vibration displacements of the capillaries were measured using a laser interferometer. The measurement results revealed that the amplification factor (the ratio of the vibration displacement at the capillary tip to that at the transducer point) of a capillary with a small radius transition between the bottleneck angle and the main taper angle was 37% higher than that of a capillary with a sharp transition, and this led to satisfactory results in terms of ball size, ball height, ball shear and stitch pull. To solve the ball lift problem for wire bonding of low-k ultra-fine-pitch devices, optimization of the capillary internal profile was attempted to improve bondability. Actual bonding responses were tested. Compared to a standard design, a capillary with a smaller chamfer angle, a larger inner chamfer and a larger chamfer diameter could increase the percentage of the intermetallic compound in the bond interface. Metal pad peeling and ball lift failures were not observed after an aging test.