共查询到20条相似文献,搜索用时 62 毫秒
1.
《Microwave and Wireless Components Letters, IEEE》2009,19(6):365-367
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Furuya A. Tagami M. Shiba K. Kikuta K. Hayashi Y. 《Electron Devices, IEEE Transactions on》2002,49(5):733-738
Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 μm minimum via size) resulting in a via resistance about 0.7 Ω. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 μm gate width. The propagation delay per inverter, which had an interconnect with 104 vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique 相似文献
3.
Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance. 相似文献
4.
Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects 总被引:3,自引:0,他引:3
《Electron Devices, IEEE Transactions on》2009,56(9):1799-1821
5.
The vertical interconnects between the components of a 3D system-on-chip (SoC) are realized by through-silicon vias (TSVs). These large global vias are a frequent performance bottleneck due to their high capacitive crosstalk. In order to reduce it, this work analyses the effect of temporal misalignment between the transitions on the signal nets of an interconnect structure and presents a technique to exploit it. The approach, based on a crosstalk-aware net-to-TSV assignment and hardware-efficient low-power codes, enables a dramatic improvement in the 3D interconnect performance. Circuit simulations show that the proposed technique reduces the delay and the noise of modern TSV interconnects by about 35%–50%, without noticeable cost. In combination with the classical bus invert coding, an additional decrease in the energy consumption by about 17% is obtained. 相似文献
6.
It is reported that 3-D interconnects fabricated with a selectively anodised aluminium process for a multilayer module package can be used to evaluate high-frequency performance. The proposed method of fabricating vertical interconnects is easier and more cost-effective than other RF MEMS processes. To transfer RF signals vertically, coaxial hermetic seal vias with characteristic 50 Omega impedances and embedded anodised aluminium vias with a solder ball attachment and flip-chip bonding were used. The optimised interconnect structure demonstrated RF characteristics with an insertion loss of less than 1.55 OmegadB and a return loss of less than 12.25 OmegadB over a broad bandwidth ranging from 0.1 to 10 OmegaGHz. Experimental results suggest that the developed technology, which is based on selectively anodised aluminium, can be applied to new 3-D packaging solutions. 相似文献
7.
Baozhen Li Timothy D. Sullivan Tom C. Lee Dinesh Badami 《Microelectronics Reliability》2004,44(3):1384-380
In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues. 相似文献
8.
Global (interconnect) warming 总被引:1,自引:0,他引:1
《Circuits and Devices Magazine, IEEE》2001,17(5):16-32
This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simultaneously, which have important implications for providing robust and aggressive deep sub-micron (DSM) interconnect design guidelines. The analysis takes into account the effects of increasing interconnect (Cu) resistivity with decreasing line dimensions and the effect of a finite barrier metal thickness. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the global-tier signal lines are investigated. Finally, the reliability implications for minimum-sized vias in optimally buffered signal nets will also be quantified 相似文献
9.
The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), kILD,eff, with k ILD,eff=kILDη/, where η is a physical correction factor, with 0<η<1. Both the spatial temperature profile along the metal lines and their average temperature rise can be easily obtained using these models. The predicted temperature profiles are shown to be in excellent agreement with the three-dimensional (3-D) finite element thermal simulation results. The model is then applied to estimate the temperature rise of densely packed multilevel interconnects. It is shown that for multilevel interconnect arrays, via density along the lines can significantly affect the temperature rise of such interconnect structures 相似文献
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Jun-Fa Mao Xiaoning Qian Zhengyu Yuan 《Microwave and Wireless Components Letters, IEEE》2001,11(1):33-35
In this work, the frequency-dependent RLGC parameters of high-speed coupled high Tc superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too 相似文献
13.
Simulation of high-speed interconnects 总被引:11,自引:0,他引:11
Achar R. Nakhla M.S. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(5):693-728
With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating frequencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper various high-speed interconnect effects are briefly discussed. In addition, recent advances in transmission line macromodeling techniques are presented. Also, simulation of high-speed interconnects using model-reduction-based algorithms is discussed in detail 相似文献
14.
《Electron Devices, IEEE Transactions on》2009,56(9):1873-1881
15.
Xiao-Chun Li Jun-Fa Mao Hui-Fen Huang Ye Liu 《Electron Devices, IEEE Transactions on》2005,52(10):2272-2279
This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically. 相似文献
16.
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs 总被引:1,自引:0,他引:1
Yan Lin Lei He Hutton M. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(2):124-133
Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA) with process variation and prerouting interconnect delay uncertainty for field-programmable gate arrays (FPGAs). Evaluated by SSTA using the placed and routed circuits, the stochastic clustering, placement, and routing reduce the mean delay by 5.0%, 4.0%, and 1.4%, respectively, and reduce the standard deviation of delay by 6.4%, 6.1%, and 1.4%, respectively for MCNC designs. The majority of improvements come from modeling interconnect delay uncertainty for clustering and from considering process variation for placement, while routing has less improvement on delay. In addition, we study the interaction between each individual design stage. When applying all stochastic algorithms concurrently, the mean delay and standard deviation are reduced by 6.2% and 7.5%, respectively. On the other hand, stochastic clustering with deterministic placement and routing is a good flow with little change to the entire flow, but the mean delay is reduced by 5.0%, the standard deviation is reduced by 6.4%, and the runtime is slightly reduced compared to the deterministic flow. Finally, while its improvement over timing is small, stochastic routing is able to reduce the total wire length by 4.5% and to reduce the overall runtime by 4.2% compared to deterministic routing. 相似文献
17.
Guoqing Hui Mikhail Nicholas A. David H. Philippe M. Eby G. 《Integration, the VLSI Journal》2007,40(4):434-446
Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node. 相似文献
18.
基于精确时延模型考虑缓冲器插入的互连线优化算法 总被引:2,自引:0,他引:2
随着VLSI电路集成度增大和特征尺寸的不断减小,连线的寄生效应不可忽略,互连线的时延在电路总时延中占了很大的比例,成为决定电路性能的主要因素.在互连时延的优化技术中,缓冲器插入是最有效的减小连线时延的方法.本文提出了一个在精确时延模型下,在布线区域内给定一些可行的缓冲器插入位置,对两端线网进行拓扑优化,并同时插入缓冲器以优化时延的多项式时间实现内的算法.我们的算法不但可以实现时延的最小化,也可以在满足时延约束的条件下,最小化缓冲器的插入数目,从而避免不必要的面积和功耗的浪费. 相似文献
19.
Alioto M. Palumbo G. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(6):484-488
In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried out that takes interconnect parasitics into account, and analytical design criteria are then derived by assuming that the MUX switches are made up of pass transistors or transmission gates, as is often done in practical cases. The design criteria turn out to be very simple (even more than those in [1] which did not consider the effect of interconnects) and independent of the adopted technology. In addition, an approximate delay expression is given to predict the achievable speed performance before actually carrying out the optimized design. The results are validated through post-layout simulations on a 90-nm CMOS process. 相似文献
20.
Rahman A. Reif R. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(6):671-678
In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution). Two limiting cases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as clock frequency, chip area, etc., are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs. The technology requirement for interconnects in 3-D integration is also discussed 相似文献