Power analysis of embedded software: a first step towards softwarepower minimization

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design-the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors-Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software. This can help in verifying if a design meets its specified power constraints. Further, it can also be used to search the design space in software power optimization. Examples with power reduction of up to 40%, obtained by rewriting code using the information provided by the instruction level power model, illustrate the potential of this idea     

Low power design for DSP: methodologies and techniques

Power dissipation is becoming a limiting factor in the realization of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design techniques are now emerging. This paper provides an overview of the techniques and methodologies that have emerged in the past few years for DSP system design. These include techniques for minimizing power at architectural and algorithmic levels including DSP programming issues. In addition, the paper indicates some potential design directions.     

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

On-chip inductance cons and pros

Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the undesirable effects of on-chip inductance are higher interconnect coupling noise and substrate coupling, challenges for accurate extraction, the required modifications of the infrastructure of CAD tools, and the inevitably slower CAD tools as compared to RC-based tools. Among the desirable effects is lower power consumption, less need for repeaters, faster signal rise time, and less delay uncertainty. The viability of design methodologies considering on-chip inductance is briefly discussed.     

CAD技术在电子封装中的应用及其发展

现代电子信息技术的发展,推动电子产品向多功能、高性能、高可靠性、小型化、低成本的方向发展,微电子封装、IC设计和IC制造共同构成IC产业的三大支柱。计算机辅助设计(CAD)作为一种重要的技术手段在IC产业中发挥了巨大作用,已广泛应用于电子封装领域。本文结合各个时期电子封装的特点,介绍了封装CAD技术的发展历程,并简要分析了今后发展趋势。     

A Full Custom Integrated Circuit for Document Analysis Systems

This paper describes the architecture and design methodology used to produce a new custom IC intended for automatic document analysis. The circuit implements the entire operative part of a dedicated microprogrammed processor for the next generation of page readers which include items such as Optical Character Recognition (OCR) and different codings for graphics and images. The chip provides a wide range of powerful functions, performing up to three operations per cycle. It includes about 10 000 transistor sites and occupies an area of 20 mm/sup 2/. A standard 6-/spl mu/m NMOS technology was used. Typical clock frequency is 2 MHz. The layout was obtained using a highly regular architecture and some automatically generated structures. New CAD tools provided an efficient and short design procedure.     

A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

VLSI计算机辅助设计框架──面向对象的DO模型及EOIDE框架的开发

本文叙述了一种新的集成电路计算机辅助设计框架的设计思想：提出了符合集成电路设计需要的新的四维数据模型，并设计了面向对象的工程数据库；提出了便于在框架中集成已开发完成的ＩＣ设计工具的松耦合的集成方式。讨论了用户管理、设计数据的版本管理以及在层次设计、多用户环境下的并发控制等在框架实施中的问题，提出了处理方案。基于上述思想，在ＨＰ／８００工作站ＵＮＩＸ操作系统下开发了集成电路设计框架ＥＯＩＤＥ（Ｅｎｔｉｔｙ－ＯｒｉｅｎｔｅｄＩＣＩｎｔｅｇｒａｔｅｄＤｅｖｅｌｏｐｍｅｎｔＥｎｖｉｒｏｎ－ｍｅｎｔ），并在框架上装入了单层门阵列设计工具（ＥＮＹＡ），设计了单层门阵列电路，结果良好。     

A Smart Power Integrated Circuit Educational Tool

This paper describes a course in Smart Power based on the introduction of an innovative educational tool-a preprocessed Smart Power integrated circuit. The methodology used to introduce students to the issue of Smart Power design, resorting to low cost standard CMOS technology is presented. The theoretical support is envisaged to provide the required knowledge to specify characteristics and performance of the most common blocks used in Smart Power and to develop skills for monolithic integration. Through design, simulation, and experimental characterization, the students were able to experience the different steps of a Smart Power project, from the power device basic switching cell mask layout to the final system prototype, in 60 hours of a one semester course. The referred Smart Power Integrated Circuit (IC) embedding analog and digital basic blocks and high-voltage transistor arrays is the key idea to the presented pedagogical methodology. Based on this Smart Power IC, different topologies required by power electronics and power management systems were implemented. A complete system illustrative example-a step-down hard-switching dc-dc regulator (buck regulator)-implemented by the students is shown and discussed.     

超高速移位寄存器单元结构设计方法

本文以高速八位移位寄存器的研制为例,介绍了一种简便可行的专用集成电路单元结构设计方法。专用集成电路的设计目前有很多方法,但都基于有先进的设计工具和较为丰富的集成电路CAD库。没有这些设计环境,使用单元结构设计方法同样可以较快地设计专用集成电路。与通常的设计相比,这种方法具有设计周期短,电路性能高,设计成本低,版图布局对称等特点,是一种较好的专用集成电路设计方法。     

A robust single phase clocking for low power, high-speed VLSIapplications

Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 μm CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level     

Happy medium [EMC CAD tools]

Electromagnetic compatibility is becoming an important element in the design of virtually all equipment and systems connected to an electrical supply. Contemporary design practice is increasingly reliant on the use of computer-based tools to realise the maximum degree of automation in the design process. This trend is set to continue. Furthermore, in the design of complex systems, interactions between different facets of the design problem make concurrent engineering practices mandatory. In practice, irrespective of its technical capabilities, ease of use and cost of deployment are critical factors in determining the success of any design tool. If a CAD package is to be widely used within industry then it must be both user friendly and capable of running quickly on modest PC platforms; at the same time, offering the user the maximum possible physical insight into the nature and magnitude of the interactions affecting the design. This article describes an approach to EMC CAD tool development, based on collaborative work between the universities of York and Nottingham, which is designed to meet these exacting requirements     

Verification of Complex Analog and RF IC Designs

Meeting performance specifications in the design of analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional A/RF design methodologies. Functionally verifying A/RF designs is a daunting task requiring a rigorous methodology. As occurred in digital design, analog verification is becoming a separate and critical task. This paper describes the verification issues faced by the A/RF designer and presents a verification methodology to address these challenges. It presents a systematic approach to A/RF verification, the concept of an analog verification engineer, how to establish the methodology, and concludes with an example     

Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling of state-of-the-art work in power reduction techniques, and also in the newly emerging area of statistical optimization applied to very large scale integration (VLSI) ICs. The lack of CAD techniques to perform multiobjective function optimization (specifically parametric yield under correlated performance metrics) is a major limitation of current CAD research. In addition, with design trends pushing towards architectures based on aggressive adaptivity and voltage scaling, CAD researchers and engineers will need to refocus efforts on enabling this type of complex design     

Wave-pipelining: a tutorial and research survey

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits     

一种用于电源管理IC的电流采样电路

利用高压集成功率集成器件,设计了一种用于电源管理IC的电流采样电路.此采样电路具有结构简单、精度高、耐高压(＞800 V)、低损耗等特点;同时实现了功率芯片的自供电功能,无需外加芯片供电电源.     

Visitor-based application analysis methodology for early design space exploration

Applications and architectures for embedded systems are becoming more and more complex. It is difficult to analyze complex embedded applications at early stages of the design flow without generic automated tools and methodologies. Consequently, application analysis under the real input conditions is becoming more and more important. Existing application analysis methodologies mainly focus on a single design objective. A general purpose application analysis methodology is required to satisfy multiple objectives of early design space exploration. This article proposes a general purpose application analysis methodology based on a visitor design pattern. High level source specifications are transformed into a trace tree representation by dynamic analysis. Trace tree representation is analyzed by using a visitor design pattern to get run-time characteristics of the application. Among other outcomes, application characterization and average inherited parallelism are key concerns in this article. Experimental results with MPEG-2 video decoder shows viability of the proposed methodology.