Carbon-Incorporated Amorphous Indium Zinc Oxide Thin-Film Transistors

We propose the use of amorphous-carbon indium zinc oxide (a-CIZO) as a channel material for thin-film transistor (TFT) fabrication. This study chose a carbon dopant as a carrier suppressor and strong oxygen binder in amorphous-indium zinc oxide (a-IZO) channel material. a-CIZO thin films were deposited using radiofrequency (RF) sputtering and postannealed at 150°C. X-ray diffraction and transmission electron microscopy analysis revealed that the film remained amorphous even after postannealing. The a-CIZO TFT postannealed at 150°C exhibited saturation field-effect mobility of 16.5 cm² V^?1 s^?1 and on–off current ratio of ～4.3 × 10⁷.     

Zinc Oxide Thin-Film Transistors Fabricated at Low Temperature by Chemical Spray Pyrolysis

We report the electrical behavior of undoped zinc oxide thin-film transistors (TFTs) fabricated by low-temperature chemical spray pyrolysis. An aerosol system utilizing aerodynamic focusing was used to deposit the ZnO. Polycrystalline films were subsequently formed by annealing at the relatively low temperature of 140°C. The saturation mobility of the TFTs was 2 cm²/Vs, which is the highest reported for undoped ZnO TFTs manufactured below 150°C. The devices also had an on/off ratio of 10⁴ and a threshold voltage of ?3.5 V. These values were found to depend reversibly on measurement conditions.     

Design of High-Performance Regioregular Polythiophenes for Organic Thin-Film Transistors

The performance of a regioregular polythiophene semiconductor for solution-processed organic thin-film transistors (OTFTs) is critically dependent on its ability to self-organize from solution and its stability against p-doping by oxygen. Structural features that promote lamellar ordering and delicately curtail the /spl pi/-conjugation of regioregular polythiophene system would enable achievement of high field-effect mobility in air. Molecular design principles and structure-property correlation studies that lead to the design of a solution-processed, all-round high-performance polythiophene semiconductor system (PQT) for OTFTs are discussed. Mobility to 0.14 cm/sup 2/ V/sup -1/ s/sup -1/ and current on/off ratio of 10/sup 7/, together with other desirable thin-film transistor (TFT) properties have been obtained with this class of organic semiconductors in OTFTs under ambient fabrication conditions.     

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage (V _ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.     

Pentacene-Based Thin-Film Transistors With a Solution-Process Hafnium Oxide Insulator

Pentacene-based organic thin-film transistors with solution-process hafnium oxide (HfOx) as gate insulating layer have been demonstrated. The solution-process HfOx could not only exhibit a high-permittivity (kappa = 11) dielectric constant but also has good dielectric strength. Moreover, the root-mean-square surface roughness and surface energy (gammas) on the surface of the HfOx layer were 1.304 nm and 34.24 mJ/cm², respectively. The smooth, as well as hydrophobic, surface of HfOx could facilitate the direct deposition of the pentacene film without an additional polymer treatment layer, leading to a high field-effect mobility of 3.8 cm²/(V middots) .     

High-Performance Self-Aligned Bottom-Gate Low-Temperature Poly-Silicon Thin-Film Transistors With Excimer Laser Crystallization

In this letter, high-performance bottom-gate (BG) low-temperature poly-silicon thin-film transistors (TFT) with excimer laser crystallization have been demonstrated using self-aligned (SA) backside photolithography exposure. The grains with lateral grain size of about 0.75 mum could be artificially grown in the channel region via the super-lateral-growth phenomenon fabricated by excimer laser irradiation. Consequently, SA-BG TFT with the channel length of 1 mum exhibited field-effect mobility reaching 193 cm²/V ldr s without hydrogenation, while the mobility of the conventional non-SA-BG TFT and conventional SA top-gate one were about 17.8 and 103 cm²/V ldr s, respectively. Moreover, SA-BG TFT showed higher device uniformity and wider process window owing to the homogenous lateral grains crystallized from the channel steps near the BG edges.     

Active Layer Thickness Effects on the On-State Currentand Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

Solution-Processed Zinc Oxide Transistors for Low-Cost Electronics Applications

Transparent conductive oxides are promising candidates for realization of transparent electronics for display applications. The use of solution-processing techniques allows for a dramatic reduction in cost per unit area of electronic functionality. As a result, there is tremendous interest in the use of solution-processed transparent conductive oxides for realization of low-cost transparent electronic systems. Zinc oxide is processable out of solution using a variety of routes, including the use of nanoparticles, nanowires, and chemical bath deposition. By optimizing the deposition processes, it is possible to realize solution-processed transparent semiconductor films offering performance that is comparable to or better than amorphous silicon, while offering the advantages of transparency. Here, techniques for fabrication of solution-processed ZnO-based transistors are reviewed, and the outlook for such technologies is discussed.      

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

Stretchable,Transparent Zinc Oxide Thin Film Transistors

Stretchable and transparent thin film transistors (TFTs) with intrisically brittle oxide semiconductors are built using a wavy structural configuration that can provide high flexibility and stretchability. After device fabrication procedures including high temperature annealing, the oxide semiconductor‐based TFT arrays can be transferred directly to plastic or rubber substrates, without an additional device process, using transfer printing methods. This procedure can avoid some of the thermal degradation problems associated with plastic or rubber substrates by separating them from the annealing procedure needed to improve the device performance. These design and fabrication methods offer the possibility of developing a new format of stretchable electronics.     

Microwave ZnO Thin-Film Transistors

We have developed ZnO thin-film transistor design and fabrication techniques to demonstrate microwave frequency operation with 2-$muhbox{m}$ gate length devices produced on GaAs substrates. Using $hbox{SiO}_{2}$ gate insulator and pulsed laser deposited ZnO active layers, a drain–current on/off ratio of $hbox{10}^{12}$, a drain–current density of 400 mA/mm, a field-effect mobility of $hbox{110} hbox{cm}^{2}!/ hbox{V}!cdothbox{s}$, and a subthreshold gate voltage swing of 109 mV/dec were achieved. Devices with Ti-gate metal had current and power gain cutoff frequencies of 500 and 400 MHz, respectively.      

Crystallization of Double-Layered Silicon Thin Films by Solid Green Laser Annealing for High-Performance Thin-Film Transistors

We report a new laser crystallization method employing double-layered amorphous-Si ( $a$-Si) thin films for solid green laser annealing (GLA) crystallization that is called GLA double-layered x'tallization (GLADLAX). Crystallization of the upper and lower $a$-Si layers of the double-layered substrate at a single laser scanning was achieved, with the upper $a$-Si becoming poly-Si with very large crystal grains and the lower $a$-Si layer becoming microcrystalline Si. Thin-film transistors using the upper layer of poly-Si that is crystallized by the method as their active channels had excellent switching performance, with their mobility exceeding 350 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$, demonstrating promising applicability of GLADLAX to thin-film electronics.      

Low-Temperature Pulsed-PECVD ZnO Thin-Film Transistors

We report high-quality ZnO thin films deposited at low temperature (200°C) by pulsed plasma-enhanced chemical vapor deposition (pulsed PECVD). Process byproducts are purged by weak oxidants N₂O or CO₂ to minimize parasitic CVD deposition, resulting in high-refractive-index thin films. Pulsed-PECVD-deposited ZnO thin-film transistors were fabricated on plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ dielectric and have a field-effect mobility of 15 cm²/V s, subthreshold slope of 370 mV/dec, threshold voltage of 6.6 V, and current on/off ratio of 10⁸. Thin-film transistors (TFTs) on thermal SiO₂ dielectric have a field-effect mobility of 7.5 cm²/V s and threshold voltage of 14 V. For these devices, performance may be limited by the interface between the ZnO and the dielectric.     

Transparent Oxide Thin-Film Transistors Composed of Al and Sn-doped Zinc Indium Oxide

We have fabricated the transparent bottom gate thin-film transistors (TFTs) using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron sputtering at room temperature, and the AT-ZIO TFT showed a field effect mobility of 15.6 $ hbox{cm}^{2}/hbox{Vs}$ even before annealing. The mobility increased with increasing the $hbox{In}_{2}hbox{O}_{3}$ content and postannealing temperature up to 250 $^{circ}hbox{C}$. The AT-ZIO TFT exhibited a field effect mobility of 30.2 $hbox{cm}^{2}/hbox{Vs}$, a subthreshold swing of 0.17 V/dec, and an on/off current ratio of more than $10^{9}$ .      

Approaching Trap-Minimized Polymer Thin-Film Transistors

Semiconducting π-conjugated polymers are the most promising candidates for flexible electronics owing to their facile processability and mechanical robustness; however, achieving steep and stable switching operations in polymer thin-film transistors (TFTs) remains a serious challenge. Herein, it is shown that whole optimizations for eliminating interfacial carrier traps throughout the conductive path are necessary in achieving TFTs showing both exceptionally sharp switching and bias-stress-free characteristics. Inverted-coplanar-type TFTs composed of a highly lyophobic amorphous perfluoropolymer gate–dielectric interfaced with a push-coated semiconducting polymer layer are manufactured. The use of the dielectric allows the establishment of bias-stress-free characteristics with minimized contact resistance. Additionally, fairly sharp on/off switching TFTs with the smallest normalized subthreshold swing can be obtained by utilizing a particular donor–acceptor copolymer that involves a self-passivation mechanism working to achieve a trap-minimized interface. These findings have opened a way for low-power and robust device operations in polymer-based flexible electronics.     

High Mobility and Stability of Thin-Film Transistors Using Silicon-Doped Amorphous Indium Tin Oxide Semiconductors

We report the fabrication of high-performance thin-film transistors (TFTs) with an amorphous silicon indium tin oxide (a-SITO) channel, which was deposited by cosputtering a silicon dioxide and an indium tin oxide target. The effect of the silicon doping on the device performance and stability of the a-SITO TFTs was investigated. The field-effect mobility and stability under positive bias stress of the a-SITO TFTs with optimized Si content (0.22 at.% Si) dramatically improved to 28.7 cm²/Vs and 1.5 V shift of threshold voltage, respectively, compared with the values (0.72 cm²/Vs and 8.9 V shift) for a-SITO TFTs with 4.22 at.% Si. The role of silicon in a-SITO TFTs is discussed based on various physical and chemical analyses, including x-ray absorption spectroscopy, x-ray photoelectron spectroscopy, and spectroscopic ellipsometry measurements.     

Self-Aligned Top-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Self-aligned techniques are often used in conventional CMOS and Si-based thin-film transistors (TFTs) technologies due to various merits. In this paper, we report self-aligned coplanar top-gate InGaZnO TFTs using PECVD a-SiN$_{x}$:H patterned to have low hydrogen content in the channel region and high hydrogen content in the source/drain region. After annealing to induce hydrogen diffusion from a-SiN$_{x}$:H into the oxide semiconductor, the source–drain regions become more conductive and yet the channel region remains suitable for TFT operation, yielding a working self-aligned TFT structure. Such fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.      

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

Bottom-Gate Gallium Indium Zinc Oxide Thin-Film Transistor Array for High-Resolution AMOLED Display

The fabrication process and the characteristics of bottom-gate $ hbox{Ga}_{2}hbox{O}_{3}{-}hbox{In}_{2}hbox{O}_{3}{-}hbox{ZnO}$ (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.