A simple method for achieving immunity to internal noise signals in thyristors

The work presents an alternative solution—with respect to the conventional cathode shunts or MOS-controlled emitter shorts—for achieving virtual immunity to the parasitic action of displacement currents in power thyristors. The simple design/technological approach developed, based upon the novel double-interdigitated or two interdigitation levels (TIL) concept with a coarse geometry, offers a fair balance between technological simplicity/cost effectiveness and overall device performance.

Based upon the presented design guidelines, two sets of gold-doped thyristors with different geometrical configurations and current/voltage-handling capabilities were produced. The measurements performed on both sets of TIL-type thyristors have shown that the devices possess an extremely high value of the maximum permissible critical rate of rise of the forward anode voltage (static dV/dt capability) even under open-gate conditions. Unlike the thyristors using conventional emitter shorts, the TIL-type devices possess a good static and dynamic turn-on/latching sensitivity and have low on-state losses at high anode current densities. The main implications of developed concepts for power thyristors design/technology are also outlined in this work.     

Characteristics of TIL GTO thyristors using no lifetime killers

The investigation reported in this work was focused on the main characteristics of the recently developed two interdigitation level (TIL) gate turn-off (GTO) thyristors, which use neither lifetime killers nor anode shorts. The advantages of these TIL GTO's with low on-state losses are outlined in comparison with their identical, yet gold-doped, counterparts. It is shown that, except for the turn-off time, the main electrical characteristics of TIL GTO's using no induced recombination centers are superior to those of similar gold-doped devices. The current-handling capability of the former under tough electrothermal ratings is also better than that of gold-doped devices up to a commutation frequency of 5 kHz. The results of this work demonstrated that sought-for benefits could be obtained in TIL GTO's which use neither induced recombination centers nor anode shorts.     

Importance of the n-base width in the turn-off performance of TIL GATT's

The influence of the n-base width on the turn-off performance of two interdigitation level (TIL) gate-assisted turn-off thyristors (GATT's) has been investigated. Devices with n-base width WnB= 250 and 360 µm, respectively, were comparatively tested. The two sets of high-power, 1.7-cm²area, gold-diffused TIL GATT's processed in identical conditions have low on-state losses, good turn-on sensitivity, and exhibit a high degree of immunity to internal noise signals. The investigations have shown that the TIL GATT's with WnB= 360 µm could possess a better efficiency of the turn-off time tqreduction in comparison with their counterparts having a thinner n base. The main physical mechanisms explaining the lack of incompatibility at the fundamental level between a larger n base and a reduced value of tqin TIL GATT's are described in detail. The results of this work show that the high blocking voltage capability, which is mainly a function of the base thickness WnBand doping, is in no way a hindrance in achieving a substantial reduction of tqin TIL GATT's with an adequate gate-assist signal.     

Current balancing in TIL GTO thyristors

Based on the advanced three-transistor model of the two interdigitation levels (TIL) GTO thyristor structure, the theory underlying the device behavior in the ON-state is developed and experimentally validated. The mechanisms underlying the current balancing between the two p-n-p-n sections (standard and quasi-nonregenerative) constituting the TIL GTO structure are disclosed. It is shown that thanks to the current balancing, the effective cathode emitter area increases with the anode current level and that the current density along the standard p-n-p-n sections lags behind the level of load current iT. The broad implications of reported theoretical/experimental results for the physics of the novel device are outlined in the communication. It is shown, e.g., that current balancing is responsible for the drastic boost of the peak interruptable anode current IATOreported for the recently developed TIL GTO thyristors.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.     

Improvement of thyristor turn-on by calculation of the gate-cathode characteristic before injection

The ohmic part of the gate-cathode characteristic of thyristors has been calculated numerically. Normal and amplifying gate structures as well as emitter shorts are included. By a simple extension of the model, the case of the dv/dt and breakover turn-on has also been treated. It is thus possible to calculate the minimal control current and voltage for a cathode side thyristor geometry and to optimize the device with respect to the turn-on process.     

Gate-assisted turn-off effect in TIL-type thyristors

The research reported in this work was focused on the turnoff performance of trial high-power gate-assisted turn-off thyristors (GATT's) based upon the novel double-interdigitated or two interdigitation levels (TIL) gate-cathode concept. The experiments were performed on high-voltage (2000 V) devices which were driven up to an anode current ofi_{T} = 500A. The test TIL GATT's were both gold-doped and normal (nongold,diffused). The investigations have shown that the application of a negative gate current of only 4 A leads to a reduction of the turn-off time iqby a factor of 3 and 4-4.5 in gold-doped and normal devices, respectively, at Tj= 100°C. At constant gate current, the dependence of tqon the anode current level tTwas found relatively weak. The additional experimental data provided in this work show clearly that sought-for benefits could be achieved by implementing the TIL pattern in power GATTs.     

Optimum design of thyristor gate—Emitter geometry

This paper describes a new method of studying the influence of the gate-emitter geometrical configuration of thyristors upon their triggering performances. This method allows, for devices of any geometrical complexity, to calculate the emitter bias voltage distribution prior to turn-on and hence to compare the behavior of these devices from a geometrical point of view. The results may be used as guide lines for the optimum design of gate-emitter configurations. As examples, precise design rules are given for standard thyristors and application to amplifying interdigited gate thyristors are outlined.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—I. Analysis and design

A rigorous analysis of the novel two-interdigitation levels gate turn-off thyristors (TIL GTOs) is performed with the aim of increasing their current-handling capability up to their limits. A closed form relationship correlating the maximum controllable anode current I_ATO with the peculiar geometry of the TIL pattern and the main technological parameters is obtained. Design rules with general validity are set out for the worst premises and correlated with the physics underlying the peculiar behaviour of TIL GTOs in various modes of operation. Based on the advanced three-transistor model of the TIL GTO structure, the basic theory underlying the device behaviour in the ‘on’ state is developed. The mechanisms of the current balancing between the two types of p-n-p-n sections (standard and quasi-non-regenerative) constituting the TIL GTO structure are disclosed. The broad implications of the current balancing on the current-handling capability of devices are presented in detail. The optimized design criteria were applied to 4 × 4 mm area, TO-220-packed TIL GTOs. The projected value of I_ATO in the worst case is 45 A, which would be the highest value of I_ATO ever reported in the literature for this class of GTOs (identical device area and case).     

Implementing the TIL Concept in high-power GTO's

This work reports the results obtained in the implementation of the novel two interdigitation level (TIL) gate-cathode configuration in high-voltage (2000 V), high-current (600 A), gate turn-off (GTO) thyristors. It is shown that the implementation of the TIL concept in high-power GTO's, while relaxing the trade-off between the doping/ width of the p base and the main electrical parameters, offers a fair balance between manufacturability ease/cost effectiveness and overall device performance. A distinct benefit obtained through the implementation of the TIL pattern in high-power GTO's is expressed by the ability of devices with an active area of only 1.7 cm²to safely switch off an anode current of 600 A with a practically usable operational turn-off gain Goffof 5-8. The low on-state voltage drop of gold-doped, high-power TIL GTO's is accompanied by a high nonrepetitive surge current capability. The trial devices possess a good latching/turn-on sensitivity accompanied by an immunity to noise (high dV/dt capability).     

A new ultra-wideband fractal monopole antenna

The paper focuses on the peculiar dynamic behaviour of the recently developed 8 mm² TO-220-packaged, high-voltage, double-interdigitated (or rwo interdigi-tation levels—TIL) GTO thyristor. This novel power device was rated under both slightly and heavily inductive resistive loads, i.e. close to the real conditions encountered in practical power circuits employing GTO thyristors. Emphasis is laid on the ability of TIL GTOs to switch safely, with minimum power losses, a certain amount of anode current under high-voltage conditions and high commutation frequencies. The merits of TIL GTO thyristors are analysed in terms of their reliability and switching efficiency, which include the total power losses (conduction and switching losses), turn-on and turn-off gains and the switching speed. It is shown that thanks to their built-in self-protective features, these novel GTOs possess an enhanced current-handling capability at commutation frequencies up to 50kHz under extremely tough load conditions. The main implications of the results for power applications are outlined.     

Computer-aided experimental investigation of the correct turn-on in thyristors with amplifying gate

A 2-dimensional computer model has been developed for the analysis of the amplifying gate thyristors correct turn-on at the auxiliary emitter prior to the main one. The results of investigation were used in the design of devices having essentially the same di/dt high capability in any possible turn-on conditions.     

A measurement technique and algorithm for determining the n-p-n and p-n-p alphas of a thyristor

A new method has been developed for accurately measuring the forward-blocking characteristics of gate-turnoff (GTO) thyristors, and for converting these characteristics into plots of n-p-n and p-n-p gain as a function of anode current and anode voltage. Specifically, anode current and gate current are measured as functions of gate-to-cathode voltage at a fixed anode voltage over several orders of magni, tude of anode current. These data are used to determine the electron and hole components of anode current, which are, in turn, used to calculate αnpnand αpnpover the entire range of anode current of interest. Examples are given that show how junction shorts, low minority-carrier lifetime in the n-base, and anomalously low n-p-n gain are diagnosed in GTO thyristors. These new procedures have successfully diagnosed the causes of gate insensitivity in 95 percent of the devices to which they have been applied.     

Efficiency of gate control in double-interdigitated (TIL) GTO thyristors

The research reported in this work was focused on the efficiency of gate control during turn-off in the recently developed double-interdigitated (TIL) GTO thyristors. The 8 mm² area, TO-220 packaged, high voltage test devices were investigated under both current and voltage input conditions. The main monitored parameters were: the peak turn-off gain K_off(max), the components of the turn-off time and the gate pulse width t_gr. During the tests the TIL GTOs were driven up to an anode current i_T = 50 A, a value equal to the non-repetitive peak on-state current (I_TSM) of these thyristors.The performed investigations have shown that these novel GTO devices possess a good efficiency of gate control expressed by: 1) low power consumption by the gate under both current and voltage drive conditions; 2) extremely high turn-off gain K_off(max), which is an increasing function of the anode current in a wide range of gate signals amplitudes and durations; 3) fast turn-off of large amounts of anode current with relatively short gate pulse widths; 4) substantial reduction of the storage time t_s and fall time t_f through adequate current or voltage drive. Design/behavioral details are given, which are useful in the implementation of the TIL concept in GTOs and other power switching devices, such as the bipolar transistors.     

A novel gate—Cathode configuration with two interdigitation levels for GTO thyristors

A new gate-cathode concept leading to a substantial improvement of the main parameters of the gate turn-off (GTO) thyristors has been developed and successfully tested on medium power devices. The distinctive feature of the novel pattern with two interdigitation levels (TIL) consists in its unique ability to bring under designer's control the processes of sweeping-out of the stored charge and of the anode current squeezing.     

The dV / dt capability of field-controlled thyristors

A detailed analysis of thedV/dtcapability of field-controlled thyristors is presented. It is demonstrated for the first time thatdV/dtinduced turn-on can occur in these devices due to gate debiasing as a result of capacitive gate current flow if a large series gate resistance is present in the circuit. A theoretical analysis of thedV/dtcapability is presented based upon this mechanism which predicts that thedV/dtcapability will decrease inversely with increasing gate series resistance at low values and become independent of the gate series resistance at very high values. The quantitative calculations of thedV/dtcapability that have been made by using this theory are in very good agreement with measurements taken on asymmetrical field-controlled thyristors fabricated from wafers of various thickness. The results obtained in this study allow the conclusion that thedV/dtcapability of field-controlled thyristors are superior to that of conventional thyristors.     

Temperature dependence of field-controlled thyristor characteristics

The dependence of the characteristics of field-controlled thyristors upon the ambient temperature has been examined in the range of -30 to 200°C. Unlike conventional thyristors, these devices have been found to continue to exhibit forward blocking capability up to the highest measurement temperature (200°C). In fact, it is shown here that the forward blocking capability as well as the blocking gain improve with increasing temperature with the usual scaling of the leakage current for power devices. The reverse blocking capability is also retained. The forward voltage drop of the device in the conducting state decreases with increasing temperature. This behavior is shown to be similar to that of conventional rectifiers and thyristors operated at high injection levels. Further, the force gate turn-off time of the devices has been found to increase with increasing temperature. This has been correlated with a measured increase in the minority-carrier lifetime. The results of this study demonstrate that field-controlled thyristors are capable of being operated at higher temperatures than conventional thyristors.     

Comparison of p-channel lateral insulated-gate bipolar transistorswith and without collector shorts

The performances of p-channel lateral insulated-gate bipolar transistors (LIGBTs) with and without collector shorts on n^- epi/n⁺ substrates are compared. The collector-shorted devices have a 4× improvement in turn-off time but about 1-V higher forward drop, due to a substantially reduced vertical current component. The addition of a buried layer on the emitter side increases the forward drop and reduces the turn-off time slightly for both types of LIGBTs. The presence of the collector shorts significantly improves the breakdown voltage but increases the percentage of the lateral current component, leading to a lower maximum gate controllable current     

Comparison of gold, platinum, and electron irradiation for controlling lifetime in power rectifiers

Recombination statistics based upon a single dominant level have been used to predict the relative characteristics of gold-diffused, platinum-diffused, and electron-irradiated silicon power rectifiers and thyristors. These calculations indicate that gold-diffused devices will have the best trade-off curve between forward voltage drop and reverse recovery time, while exhibiting the highest leakage currents. Electron-irradiated devices are predicted to have the worst trade-off curve among the three cases and twice the leakage current of platinum-diffused devices. The leakage current of platinum-diffused devices is shown to be an order of magnitude lower than gold-diffused devices. The measured characteristics of gold-diffused, platinum-diffused, and electron-irradiated power rectifiers are shown to be in good agreement with these calculations. The results are also shown to be applicable to power thyristors.     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.