1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

1/f noise studies in uncooled narrow gap Hg1−xCdxTe non-equilibrium diodes

We have studied the 1/f noise current in narrow gap semiconductor heterostructure diodes fabricated in mercury cadmium telluride (HgCdTe) and designed to operate in a non-equilibrium mode at room temperature. HgCdTe heterostructure diodes exhibit Auger suppression giving current-voltage characteristics with high peak-to-valley ratios (up to 35), and low extracted saturation current densities (e.g., 20 Acnr⁻² at 10 pm at 295K) but high 1/f knee frequencies (e.g., 100 MHz at 10 μm at 295K). A comparison is made with the noise levels found in room temperature non-equilibrium mode heterostructure InAlSb/InSb diodes. The devices are being used at high frequencies for CO₂ laser heterodyne detector demonstrators. For the devices to be useful in low frame-rate imaging arrays, the 1/f noise level must be sufficiently low that the signal is not swamped. Ideally, the knee frequency should be below the frame rate. The relationship between the noise current and reverse bias voltage, current density, and temperature will be examined in order to attempt to identify the principal 1/f generation mechanisms.     

Temperature dependence of 1/f noise in Hg1-xCdxTe MIS infrared detectors

We measured 1/f noise on Hg_0.71Cd_0.29Te Metal-Insulator-Semiconductor (MIS) infrared detectors operated over the temperature range of 40 K to 90 K under 300 K Infrared (IR) radiation. The purpose of the study was to identify the sources of 1/f noise, especially in relation to the dark current. The devices were operated in the correlated double sampling mode where the voltage across the MIS capacitor was sampled at empty potential well and right after the accumulation of minority carriers in the well due to IR radiation generation. The noise power spectral density for the charge integrated in the MIS well was investigated in relation to the dominant component of dark current. At lower temperatures T⩽65 K, the charge noise power spectral density was found to depend quadratically on the dark current. At higher temperatures, this quadratic dependence did not exist. We attribute the dark current to a mixture of tunneling and depletion-region-originated minority carrier generation which seems to be responsible for 1/f fluctuations in these structures for temperatures below 65 K     

Low-frequency noise in thick-film resistors due to two-steptunneling process in insulator layer of elemental MIM cell

In this paper, it is assumed that low-frequency noise source in thick-film resistors are fluctuations of the trap occupations by electrons, tunneling through insulator layer of the elemental cell. Two conducting particles separated by a thin insulating layer form the elemental cell (MIM structure). Trap charge fluctuations are modulating the MIM cell barrier, thus modulating the tunneling current and barrier resistance. A low frequency noise model is proposed under the assumption that the space distribution of traps in thick-film resistor is symmetrical with respect to the central plane of the MIM cell. Numerical results show that in the presence of small number of traps in insulator layer of the elemental cell, 1/f noise is exhibited in a narrow frequency range (4-5 decades). A model is applied on the experimental results for noise in thick-film resistors and a method of evaluation of the trapping state's parameters is discussed based on noise measurements     

Improvement on 1/f noise properties of nitrided n-MOSFETs bybacksurface argon bombardment

The 1/f noise properties of nitrided MOSFETs bombarded by low-energy (550 eV) argon-ion beam are investigated. It is found that after bombardment, 1/f noise, and its degradation under hot-carrier stress are reduced, and both exhibit a turnaround behavior with bombardment time for a given ion energy and intensity. The physical mechanism involved is probably enhanced interface hardness resulting from bombardment-induced stress relief in the vicinity of the oxide/Si interface. Moreover, from the frequency dependence of the noise, it is revealed that the nitrided devices have a nonuniform trap distribution increasing toward the oxide/Si interface which can be modified by the backsurface bombardment     

A model for 1/f noise in diffusion current based on surfacerecombination velocity fluctuations and insulator trapping

In this paper we present a new model for low frequency 1/f noise in semiconductor diodes. The model describes noise in diffusion current due to fluctuations in surface recombination velocity. The fluctuations in surface recombination velocity are in turn caused by insulator trapping. We examine the model's predictions for 1/f noise and its dependence on device geometry, temperature, surface potential, majority carrier concentration, and trap energy. Example calculations are performed for narrow band gap HgCdTe (E_G=0.125 eV at 77 K), for which this mechanism should be relevant     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

1/f noise in HgCdTe photodiodes

1/f noise in HgCdTe photodiodes has been attributed to a variety of sources, most of which are associated with some form of excess current. At DRS, we have measured the 1/f noise in vertically integrated (VIP) and high-density vertically integrated photodiodes (HDVIP), over a wide range of compositions and temperature, for strictly well-behaved diffusion current limited operation. It is found that (1) the 1/f noise current is directly dependent on dark current density; (2) material composition and temperature are irrelevant, except in as much as they determine the magnitude of the current density; (3) in high-quality diodes, the 1/f noise is independent of background flux; and (4) surface passivation is relevant. These observations have been compared to the 1/f noise theory of Schiebel, which uses McWhorter’s fluctuation of the surface charge tunneling model to modulate diode diffusion current. Agreement is obtained with Schiebel’s theory for realistic surface trap densities in the 10¹²/cm² range, which will obviously be characteristic of the passivation used. The relevance of this work relative to high operating temperature phtodiodes is discussed.     

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO₂ gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO₂ devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO₂ system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.     

Resonance transfer of charge carriers in Si/CaF<Subscript>2</Subscript> periodic nanostructures via trap states in insulator layers

A model of the resonance-tunneling transport of charge carriers via discrete-level traps in insulator layers in Si/CaF₂ periodic low-dimensional structures is proposed. Upon application of the external bias voltage to the structure, the resonance-tunneling transport occurs in the cases when the energy of the charge carriers in Si wells coincides with the energy of the trap level in CaF₂ layers. It is shown that filling of the traps and violation of the conditions for the resonance-tunneling transport of charge carriers via the trap level, which take place when the energy of the carriers in the wells exceeds the energy of the trap state in the insulator, result in a drop in the current through the structure; thus, a region of negative differential resistance is formed in the current-voltage characteristics of Si/CaF₂ periodic structures. Simulation of this effect shows that devices based on these structures may operate in a wide range of temperatures from 77 to 300 K. Another advantage is their compatibility with silicon integrated-circuit technology.     

Single‐Electron Tunneling through Molecular Quantum Dots in a Metal‐Insulator‐Semiconductor Structure

A sigle‐electron tunneling (SET) in a metal‐insulator‐semiconductor (MIS) structure is demonstrated, in which C₆₀ and copper phthalocyanine (CuPc) molecules are embedded as quantum dots in the insulator layer. The SET is found to originate from resonant tunneling via the energy levels of the embedded molecules, (e.g., the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO)). These findings show that the threshold voltages for SET are tunable according to the energy levels of the molecules. Furthermore, SET is observable even near room temperature. The results suggest, together with the fact that these properties are demonstrated in a practical device configuration, that the integration of molecular dots into the Si‐MIS structure has considerable potential for achieving novel SET devices. Moreover, the attempt allows large‐scale integration of individual molecular functionalities.     

Neutron irradiation of insulated gate field effect transistors

Insulated gate field effect transistors and polysilicon-gated capacitors were irradiated with fast (10 keV <E < 2 MeV) neutrons. As expected, damage to the bulk silicon was detected as a degradation in the minority carrier lifetime. Optically assisted electron injection was employed for the first time to examine neutral electron trap and fixed positive charge generation in the gate insulator of the devices. While fixed positive charge densities of ≤6 x 10¹⁰ cm⁻² were detected, little or no neutral electron trap generation was observed. The small density of coulombic defects observed in the insulator could be accounted for fully by the known flux of gamma rays associated with the neutron irradiation process. This indicates that fast neutrons passing through a thin gate oxide do not produce significant amounts of damage in the oxide. Somewhat surprisingly, it was found that 1.5 keV X-rays created similar lifetime degradation effects in the bulk silicon, as did fast neutrons, even though this photon energy is not believed to be capable of producing bulk damage in the form of atom displacement in either the semiconductor or the insulator. The minority carrier lifetime of the silicon could be restored to initial values following either neutron or x-ray exposure by annealing in H₂ for 30 min at 400° C.     

The investigation into charge degradation of MIS structures under strong electric field by a method of controlled current load

A new method for studying charge degradation of MIS structures by applying a controlled current load to the structure and taking the time dependence of the voltage is suggested. It allows designers (without switching the structure) to monitor changes in the charge state of MIS structures under the conditions when the capacitance is charged and the charge is injected into the insulator. Charge degradation of metal-PSG-passivated thermal silicon dioxide-insulator structures was studied. It was found that both the SiO₂ space charge and the density of fast surface states generated by tunnel electron injection from the SiO₂ electrode decrease once current load has disappeared.     

Low frequency gate noise in a diode-connected MESFET: measurementsand modeling

The low frequency Schottky diode noise has been investigated in GaAs power MESFETs. For those devices, gate noise spectra are generally composed of 1/f and shot noise contributions. We have observed an increase by two orders of magnitude of the noise level when MESFETs are submitted to rf life-test. The increase of the 1/f noise can be explained by a modification of the gate space charge region extension. This interpretation is sustained by a reduction of the drain current transient magnitude and the inherent active trap density. A correlation is assumed between the increase of the shot noise level after rf life-test and a micro-plasma formation. Both 1/f noise and shot noise evolution might originate in a local increase of the electric field in the vicinity of the gate in drain access region. We have demonstrated that LF gate current noise is an early indicator of damage mechanisms occurring at the gate-semiconductor and passivation-semiconductor interfaces of the devices     

On the influence of substrate cleaning method and rapid thermal annealing conditions on the electrical characteristics of Al/SiNx/SiO2/Si fabricated by ECR-CVD

We investigate the influence of the used cleaning method and rapid thermal annealing (RTA) conditions on the electrical characteristics of MIS devices based on SiN_y:H/SiO_x dielectric stack structures fabricated by electron-cyclotron-resonance plasma assisted chemical vapour deposition (ECR-CVD). We use capacitance–voltage (C–V) technique to study charge trapped in the insulator, Deep Level Transient Spectroscopy (DLTS) to study the trap distributions at the interface, and conductance transient (G–t) technique to determine the energy and geometrical profiles of electrically active defects at the insulator bulk as these defects follow the disorder-induced gap state (DIGS) model.     

Characterization of the switching in tunnel MISS devices

The observed bistable characteristics of metal-insulator-silicon switch (MISS) devices with moderate epi-layer doping levels are proven to be controlled by trap assisted tunneling. The switching current and the switching voltage are shown to depend on the reverse saturation current of the MIS substructure and on fabrication parameters (insulator thickness and epi-layer doping level). A method to obtain the metal-semiconductor barrier height, the injection factor at the interface and the trap density in the insulator is presented. The results have been applied to characterize AlSiO₂Si(n)Si(p⁺) structu in which the switching point and the reverse saturation current have been measured. The observed dispersion in the values of the current can be explained by assuming a unique value of the barrier height and the trap density for all devices, allowing the values of the tunneling damping factors to be different from those obtained in the two-band model, which validity is also discussed.     

Capacitance-voltage characteristics of Semiconductor-Insulator-Semiconductor (SIS) structure

The ideal low- and high-frequency capacitance-voltage curves of a semiconductor(2)-insulator-semiconductor(1) (SIS) structure were first calculated with the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) as parameters. The effects of fixed oxide charge and interface trap charge on the low and high frequency capacitance-voltage curves were also calculated. It was found that the fixed oxide sheet charge density with its centroid and the order estimation of the interface trap charge density with its effective type in addition to the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) could be estimated from measured low and high frequency capacitance-voltage curves of an SIS structure.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

Characterization of low 1/f noise in MOS transistors

By careful processing MOS transistors have been fabricated with a low value of the interface states density (2 × 10¹⁰/cm²eV). Consequently the1/fnoise in these devices is low and in the same order of magnitude as for junction FETs. The experimental values of the equivalent noise voltage and the equivalent noise current are compared to an expression derived from straight physical arguments. From the comparison it is concluded that the noise equivalent voltage in saturated operation is proportional to the effective gate voltage, the interface state density, and inversely proportional to the gate input capacitance. Moreover, it is concluded that a proper heat treatment not only reduces the number of states but also removes the near bandedge peaks, which usually appear in the trap distribution function.     

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10¹⁰cm^-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm². Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10¹⁰cm^-2.