Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

Non-Volatile Memories for Removable Media

NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. When compared to a hard disk drive, a limitation of the Flash memory is the finite number of erase/write cycles: most of commercially available NAND products are guaranteed to withstand 10$^{5}$ programming cycles at most. As a consequence, special care (remapping, bad block management algorithms, etc.) has to be taken when hard-drive based, read/write intensive applications, such as operating systems, are migrated to Flash-memory based devices. One of the basic requirements of the consumer market for data storage is the portability of stored data from one device to the other. Flash cards are the actual solution. A Flash card is a nonvolatile “system in package” in which a NAND Flash memory is embedded with a dedicated controller. This paper presents the basic features of the NAND Flash memory and the basic architecture of Flash cards. We provide an outlook on opportunities and challenges of future Flash systems.      

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Future challenges of flash memory technologies

Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.     

基于NAND Flash的海量存储器的设计

针对存储系统中对存储容量和存储带宽的要求不断提高,设计了一款高性能的超大容量数据存储器。该存储器采用NAND Flash作为存储介质,单板载有144片芯片,分为3组,每组48片,降低了单片的存储速度,实现了576 Gbyte的海量存储。设计采用FPGA进行多片NAND Flash芯片并行读写来提高读写带宽,使得大容量高带宽的存储器得以实现。针对NAND Flash存在坏块的缺点,提出了相应的管理方法,保证了数据的可靠性。     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings.The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level.     

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase–Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase–Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.     

NAND Flash与AT91RM9200的接口设计

以三星公司的与非型闪存(NAND Flash)器件K9K8G08U0A为例,介绍了NAND Flash的存储结构和接口信号以及AT91RM9200对NAND Flash的接口支持,分析了NAND Flash两种接口方式的优缺点,阐述了AT91RM9200对NAND Flash的初始化过程,重点以表格形式说明了接口时序的设计,最后对坏块的概念和ECC校验算法原理做了简单的介绍。NAND Flash的复用I/O接口为更新更高密度的器件提供了相同的引线,使得系统的扩展性大大提高。     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

基于SOPC的大容量高速数据存储系统设计

当前的先进动态测试系统往往需要高速高精度的采集前端,如何实现对大量实时数据的高速存储成为研究热点.在此背景下本文提出一种实现大容量高速存储系统的设计方案.存储模块是由NAND Flash存储芯片组成的4X4存储阵列,以FPGA为载体的SOPC系统作为存储模块的控制核心.根据NAND Flash芯片结构特性,采用位扩展和...     

基于FPGA和NAND Flash的存储器ECC设计与实现

针对以NAND Flash为存储介质的高速大容量固态存储器,在存储功能实现的过程中可能出现的错“位”现象,在存储器的核心控制芯片,即Xilinx公司Virtex-4系列FPGA XC4VLX80中,设计和实现了用于对存储数据进行纠错的ECC算法模块。在数据存入和读出过程中,分别对其进行ECC编码,通过对两次生成的校验码比较,对发生错误的数据位进行定位和纠正,纠错能力为1 bit/4 kB。ECC算法具有纠错能力强、占用资源少、运行速度快等优点。该设计已应用于某星载存储系统中,为存储系统的可靠性提供了保证。     

A New Digital Echo Canceler for Two-Wire Full-Duplex Data Transmission

A new approach to echo canceling for two-wire fullduplex data transmission is proposed. The canceling signal is directly synthesized from the binary data, using a transversal filter approach, and the usual multiplications are replaced by additions and subtractions, thus allowing efficient operation of a large number of taps as required for the canceling of distant echoes. As a specific application, a system processing one sample per baud is discussed where timing signals at both communicating stations are assumed to be synchronized. A stochastic adjustment gradient-type algorithm is used for both training and adaptive tracking of the canceler. It is shown that convergence does not depend on intersymbol interference, timing phase, carrier phase, or the energy ratio of the local to the received signal, but is a function only of the number of taps. Convergence time is proportional to that number, and the optimum step size for fastest convergence is equal to the reciprocal of the number of taps. The residual fluctuation noise is proportional to that part of the mean-square (MS) error which cannot be reduced by the canceler and is a simple function of the product of the tap signal and the step size. The predicted convergence properties are verified by simulation results. Finally, it is shown how such an echo canceler might be used to allow two-wire full-duplex transmission for data rates as high as 4800 bit/s.     

大容量NAND Flash K9T1G08UOM在网络存储中的应用

针对嵌入式系统对存储的需求，提出了基于大容量NAND Flash的存储方案。简要介绍NAND Flash器件K9T1G08UOM及其编程特点，并讨论了网络存储应用的存储策略和数据可靠性方面的考虑，设计并实现了网络数据流的NAND Flash存储。     

Cochannel interference reduction in optical PPM-CDMA systems

A multiple-user interference reduction technique is proposed for optical code-division multiple-access (CDMA) systems. Data symbols from each user are encoded using a pulse-position modulation (PPM) scheme before multiplexing. Modified prime sequences are adopted as the signature codes in the multiplexing process. An interesting property of this code is the uniformity of the cross correlation among its sequences. This property is the main key in constructing the multiple-access interference canceler. In addition to its simplicity, this canceler offers a great improvement in the error probability as compared to the system without cancellation. A simple modification to this canceler that enhances its performance is proposed as well     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device,this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory(NUC-CTM) device with virtual-source NAND-type array architecture,which can effectively restrain the second-bit effect(SBE) and provide 3-bit per cell capability.Owing to the n~- buffer region,the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between ...     

Multipath reduction using constant modulus conjugate gradienttechniques

A conjugate-gradient (CG) constant-modulus adaptive processor is proposed. For the generalized sidelobe canceler (GSC) signal processing configuration, this algorithm, CG-GSC, exhibits improved convergence over previous methods. Theoretical expressions are presented for convergence and weight update of a linearly constrained constant modulus generalized sidelobe canceler. Theoretical expressions are then derived for the conjugate direction vectors. These vectors are used to update the filter weights for a conjugate gradient adaptation rule. A simulation study of the conjugate adaptation rule reveals the increase in convergence rate for the generalized sidelobe canceler. Performance comparisons of the CG-GSC and a first-order gradient GSC for a BPSK signal with multipath and white noise interference indicate that the CG-GSC adaptation rule not only increases convergence by a factor of five compared to the first-order gradient GSC, but in some instances improves the bit error rate of the demodulated BPSK signal     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.