可编程细胞自动机伪随机序列发生方法

可编程细胞自动机不仅具有细胞自动机组成单元的简单规则性、单元之间作用的局部性和信息处理的高度并行性等特性,而且具有动力学行为的复杂变化性.基于具有不可约特征多项式的规则90/150加性细胞自动机的同构特性,本文提出了可编程细胞自动机伪随机序列发生方法,其系统的结构参数随时间变化而变化,从而使得系统具有复杂的动力学行为.计算机模拟实验表明基于可编程细胞自动机的伪随机序列发生方法实现简单,产生的伪随机序列具有周期大、速度高和随机统计特性好等优点.     

基于二维细胞自动机的图像加密技术

将二维细胞自动机(CA)的数学原理与图像加密技术相结合,提出了一种新的图像加密算法.研究结果表明,该算法具有简单易实现、安全性高、密钥量大、良好的雪崩效应以及扩散与混淆性质、运算简单和加密速度快等特点.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing

To facilitate test vector generation for high-speed circuits, we present the design and circuit simulation of parallel pseudorandom number generators in GaAs technology. These PRNGs are based on hybrid cellular automata (CA) in which mixtures of local rules are employed in one dimensional arrays, with minimal delay due to having only local wiring between neighboring cells. HSPICE simulations of these circuits demonstrate that they operate at a clock frequency above 1 GHz. Delay simulations indicate that GaAs PRNGs based upon linear feedback shift registers, in contrast with hybrid CAs, exhibit a degradation in clock frequency due to the effects of global interconnects, and that this degradation increases with the register length.This work was supported by Micronet, by the Canadian Microelectronics Corporation, and by the Natural Sciences and Engineering Research Council of Canada.     

On behavior of two-dimensional cellular automata with an exceptional rule under periodic boundary condition

This article deals with the behavior of two-dimensional(2-D) cellular automata(CA) with a special rule under periodic boundary condition by using matrix algebra.The important characteristics of CA have been studied,such as Garden of Eden(GOE),maximal transient length,maximal cycle length and so forth.Several necessary and sufficient conditions are provided,which guarantee a given configuration of being a GOE in different cases.Besides,algorithms are proposed to obtain the number of GOEs,the maximal transien...     

Analytical method for cell displacement defect quantum-dot cellular automata primitive

Quantum-dot cellular automata (QCA) is an emerging computational paradigm which can overcome scaling limitations of the existing complementary metal oxide semiconductor (CMOS) technology. The existence of defects cannot be ignored, considering the fabrication of QCA devices at the molecular level where it could alter the functionality. Therefore, defects in QCA devices need to be analyzed. So far, the simulation-based displacement defect analysis has been presented in the literature, which results in an increased demand in the corresponding mathematical model. In this paper, the displacement defect analysis of the QCA main primitive, majority voter (MV), is presented and carried out both in simulation and mathematics, where the kink energy based mathematical model is applied. The results demonstrate that this model is valid for the displacement defect in QCA MV.     

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata(QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder(ESDBA) is 26% faster than the carry flow adder(CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder(EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead(CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of(N-1)+3.5 clock cycles compared to the N*One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.     

A structure and technique for pseudorandom-based testing of sequential circuits

Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structure and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.     

A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata

The Quantum-dot cellular automata (QCA) is a novel nanotechnology, promising extra low-power, extremely dense and very high-speed structure for the construction of logical circuits at a nanoscale. In this paper, initially previous works on QCA-based FPGA’s routing elements are investigated, and then an efficient, symmetric and reliable QCA programmable switch matrix (PSM) interconnection element is introduced. This element has a simple structure and offers a complete routing capability. It is implemented using a bottom-up design approach that starts from a dense and high-speed 2:1 multiplexer and utilise it to build the target PSM interconnection element. In this study, simulations of the proposed circuits are carried out using QCAdesigner, a layout and simulation tool for QCA circuits. The results demonstrate high efficiency of the proposed designs in QCA-based FPGA routing.     

Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults

This paper presents a combinatorial method of evaluating the effectiveness of linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSR) as generators for stimulating faults requiring a pair of vectors. We provide a theoretical analysis and empirical comparisons to see why the LHCA are better than the LFSRs as generators for sequential-type faults in a built-in self-test environment. Based on the concept of a partner set, the method derives the number of distinctk-cell substate vectors which have 2^2k , 1k[n/2], transition capability for ann-cell LHCA and ann-cell LFSR with maximum length cycles. Simulation studies of the ISCAS85 benchmark circuits provide evidence of the effectiveness of the theoretrical metric.This work was supported in part by Reserach Grants No. 5711 and No. 39409 and a Strategic Grant from the Natural Sciences and Engineering Research Council of Canada and by an equipments loan from the Canadian Microelectronics Corporation.A preliminary version of this paper is partially presented at theIEEE ISCAS'94, May 1994.     

An efficient design of CORDIC in Quantum-dot cellular automata technology

Power dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology, with extremely small feature size and ultralow power consumption comparing with transistor-based technology. Anteriority, basic level-triggered flip-flop designs based on QCA implementation were examined. In this paper, we utilize the unique QCA characteristics and clock zones to design falling edge-triggered J-K flip-flop that is stable and practical. Simulation with the QCADesigner simulator is performed to verify the functionality of the proposed falling edge-triggered flip-flop. This paper also explores the design of counters. Synchronous counters are designed with several different bit sizes and simulation results demonstrate the validity of them.     

在基于LFSR重播种的压缩环境下同时降低测试数据量和测试功耗

集成电路测试中过高的测试功耗和日益增长的测试数据量是半导体工业面临的两大问题。本文提出了一种在基于线性反馈移位寄存器重播种的压缩环境下基于扫描块的测试向量编码方案。同时,本文也介绍了一种新颖的扫描块重聚类算法。本文的主要贡献是给出了一种灵活的测试应用框架,它能够极大地减少扫描移位期间的跳变个数和经由LFSR重播种生成的确定位的数目。因此,文中方案能够极大地降低测试功耗和测试数据量。在ISCAS’89基准电路上使用Mintest测试集进行的实验表明,本文方法能够减少72%-94%的跳变,并且能获得高达74%-94%的测试压缩率。     

对称三值元胞自动机的特征化表示

本文提出对称三值系统中的元胞自动机(CA_-3)的特征化表示方法.所有采用相加性规则的CA_-3均可用一个对称三值特征矩阵来表达.在此基础上,本文在最大长度和吸引子等方面对CA_-3 和二值元胞自动机进行了比较,并发现CA_-3 在演变过程中存在诸如正负对称性等新的特性.     

A client‐side design and implementation for push to talk over cellular service

This paper proposes a client architecture for the push to talk over cellular (PoC) service based on the open mobile alliance (OMA) PoC specifications v1.0 release. We show that most standard VoIP modules can be reused for the PoC client, and the VoIP software can be easily extended to support PoC service. Then we present the detailed message flows between the PoC client and other network entities in the PoC system. A PoC client prototype has been implemented in the Industrial Technology Research Institute (ITRI) and National Chiao‐Tung University (NCTU) Joint Research Center. Copyright © 2006 John Wiley & Sons, Ltd.     

A new design of QCA‐based nanoscale multiplexer and its usage in communications

Quantum‐dot cellular automata (QCA) is one of the proposed nanotechnologies in the electronics industry, which offers a new construction for scheming digital circuits with less energy consumption on the nanoscale and possibly can be an appropriate replacement of complementary metal‐oxide semiconductor (CMOS) technology. Nanocommunication in QCA has attracted a wide range of researcher's attention. However, there is still a broad scope to design QCA‐based architecture for nanocommunication. The multiplexer is hugely used in the telecommunication system and transmits multiple data at the same time. Therefore, in this paper, a useful structure to implement a 2 to 1 multiplexer based on the novel XOR gate is presented and is used as a module to implement the 4 to 1 and 8 to 1 multiplexers. Simulations using QCADesigner tool are done to check the performance of the suggested designs. The 2 to 1, 4 to 1, and 8 to 1 QCA multiplexer structures utilize 22, 92, and 260 cells and consume 0.03, 0.12, and 0.40 μm² of area, respectively. They have shown that the suggested designs have stable and applicable structures regarding area, cost, and complexity.     

A novel method for lossless image compression and encryption based on LWT,SPIHT and cellular automata

In this paper, a novel method for lossless image encryption based on set partitioning in hierarchical trees and cellular automata. The proposed encryption method embeds the encryption into the compression process, in which a small part of the data is encrypted quickly, while maintaining the good coding characteristics of set partitioning in hierarchical trees (SPIHT). The proposed encryption system adopts three stages of scrambling and diffusion. In each stage of encryption, different chaotic systems are used to generate the plaintext-related key stream to maintain high security and to resist some attacks. Moreover, the channel length of the coded-and-compressed color image is more uncertain, resulting into higher difficulty for attackers to decipher the algorithm. The experimental results indicate that the length of bitstream is compressed to 50% of the original image, showing that our proposed algorithm has higher lossless compression ratio compared with the existing algorithms. Meanwhile, the encryption scheme passes the entropy analysis, sensitivity analysis, lossless recovery test, and SP800-22 test.     

A novel nonnegative decomposition method and its application to 2-D digital filter design

In designing two-dimensional (2-D) digital filters in the frequency domain, an efficient technique is to first decompose the given 2-D frequency domain design specifications into one-dimensional (1-D) ones, and then approximate the resulting 1-D magnitude specifications using the well-developed 1-D filter design techniques. Finally, by interconnecting the designed 1-D filters one can obtain a 2-D digital filter. However, since the magnitude responses of digital filters must be nonnegative, it is required that the decomposition of 2-D magnitude specifications result in nonnegative 1-D magnitude specifications. We call such a decomposition the nonnegative decomposition. This paper proposes a nonnegative decomposition method for decomposing the given 2-D magnitude specifications into 1-D ones, and then transforms the problem of designing a 2-D digital filter into that of designing 1-D filters. Consequently, the original problem of designing a 2-D filter is significantly simplified.     

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits

This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path lengths in the clocking network. We perform numerical simulations of basic building blocks using two different simulation engines available in the QCADesigner tool. We assume that the phase shifts are characterized by a Gaussian distribution with a mean value of , where i is the clock number and a standard deviation, σ, which is varied in each simulation. Our results indicate that the sensitivity of building blocks to phase shifts depends primarily on the layout while the reliability of all building blocks starts to drop once the standard deviation, σ exceeds 4°. A full adder was simulated to analyze the operation of a circuit featuring a combination of the building blocks considered here. Results are consistent with expectations and demonstrate that the carry output of the full adder is better able to withstand the phase shifts in the clocking network than the Sum output which features a larger combination of the simulated building blocks.