Injection Locking in Concurrent Dual-Frequency Oscillators

In a separate paper, the authors show that a nonlinear active core with a fourth-order resonator can generate two stable independent frequencies simultaneously. In this paper, the effect of injecting two frequencies into such a concurrent dual-frequency oscillator is analyzed and experimentally verified. It is shown that, for weak injection, the effect of injection at one frequency is decoupled from the effect of injection at the other frequency. The differential equation describing the effect of injection at either of the two frequencies is similar to the Adler's injection-locking equation for single-frequency oscillators. A theoretical analysis for a linear array of coupled concurrent dual-frequency oscillators is provided. It is shown that a linear phase progression at both frequencies can be achieved independently by detuning the array's end elements. Dual-frequency quadrature signal generation using two coupled concurrent dual-frequency oscillators is also demonstrated. To verify the theoretical derivations, an integrated circuit in a 0.18-$mu$m SiGe BiCMOS process is designed and fabricated. Measurement results closely match the theoretical predictions. The application of concurrent coupled oscillator array in dual-frequency beam forming with steering capability is also demonstrated.      

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 $mu$m digital CMOS process operates from 0.5 to 2.5$~$GHz. At 1.5$~$GHz, the proposed PLL achieves 1.9$~$ ps long-term rms jitter and a worst case supply-noise sensitivity of ${-}$28$~$dB (0.5$~$rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.      

Quasi-Optimum Digital Phase-Locked Loops

Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line. Additional simplifications are made that permit the application of the Kalman filter algorithms to determine the minimum mean-square error (MSE) loop filter. Consideration is given to sampling rate and implementation requirements. Performance is evaluated by a theoretical analysis and by simulation. Theoretical and simulated results are discussed and a comparison to analog results is made.     

Voltage Pump Phase-Locked Loops

This paper is concerned with the phase-locked loop with Voltage Pump Phase Frequency Detector (VPPFD) and resolves the differences in explanation about its somehow peculiar behavior appearing in the literature.     

CMOS锁相环电路

本文论述了一种CMOS的数字频率变换锁相环电路,内部由电流控制延迟单元和施密特整形电路组成的压控振荡器、鉴频鉴相器、电荷泵滤波器及分频电路组成.文中从原理及实用设计的角度给出了论述,着重讨论了系统的稳定性、收敛速度与稳态误差.     

Designing Phase-Locked Oscillators for Synchronization

Phase-locked oscillators (PLO's) have two main areas of application: demodulation and synchronization. In this tutorial paper, a simplified approach to designing PLO's for synchronization is described. In particular, some tradeoffs which can be made between such characteristics as capture range, jitter attenuation, time to lock, and phase offset are presented. As examples of this approach, the method is applied to three circuits in a Picturephone^®video coder-decoder (CODEC). The application of an optimum phase comparator is also described.     

Stability Criteria for Phase-Locked Oscillators

Stability criteria for negative conductance oscillators or amplifiers are derived in terms of the total circuit admittance. A figure of merit for phase locking at small injected powers is derived. The influence of large injected signals is studied. The conclusions drawn from the calculations are in good qualitative agreement with experimental observations on phase-locked IMPATT-diode oscillators.     

Burst Synchronization of Phase-Locked Loops

Locking a phase-locked loop (PLL) with a sinusoid that is 100-percent AM modulated by a low-duty cycle square wave (i.e., comes in bursts) is an old and well-known technique. Despite this, certain aspects of the technique have not been systematically considered. One of the most important aspects is how to avoid sidelockan undesired mode where the loop locks to a frequency other than the sinusoid's frequency. In this paper, we explain how sidelock arises, how it can be avoided and how to provide a good lock while still avoiding sidelock. Throughout the paper our emphasis is on the situation, that is usually not considered, where the sinusoid's frequency can be considerably different than the center frequency of the voltagecontrolled oscillator (VCO).     

Synthesis of Distributed Phase-Locked Oscillators

This paper describes a type of distributed oscillator which combines the functions of distributed amplifiers (DAs), distributed transversal filters (DTFs), and distributed mixers (DMs). Nonlinear feedback of the kind used in mode-locked laser (MLL) systems is used in order to obtain phase locking between the resonant frequencies within the oscillator. The theory of operation is given and a tuning procedure for the tap weights of the distributed oscillator aimed at achieving a desired state of oscillation is presented. The impact that the nonideal components of the oscillator have on its performance is discussed. Through simulation it is shown that the effects of transmission line loss, uneven tap weight spacing and terminal impedance mismatch can be mitigated by properly adjusting the tap weights of the oscillator. Examples of waveform synthesis are given in which different periodic waveforms are produced by the oscillator including those found in an MLL and a waveform suitable for impulse based ultra-wideband systems.      

一种基于ADS和Matlab的锁相环电路设计方法

研究了基于ADS的锁相环电路的设计,针对该软件对仿真输出数据处理能力不足的问题,提出了一种利用Matlab对ADS仿真输出数据进行进一步处理的方法,通过对基于锁相环的线性调频信号产生电路的设计和仿真,证明了该方法的可行性和实用性。     

Quantization Effects in All-Digital Phase-Locked Loops

This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO). The delta-sigma modulator placed at the DCO input refines the frequency quantization and adds another source of in-band PLL noise. Interestingly, the higher the modulator order, the higher this source of in-band phase noise. A method for the estimation of all the quantization noise contributors is provided, which is proven by mixed-mode simulations.     

On Frequency Sweeping in Phase-Locked Loops

The following experimental study describes a new representation of the behavior that a second-order phase-locked loop (PLL) shows in the presence of linear frequency sweeping. This paper differs from previously published results in that it presents a general experimental analysis of the PLL during a sweep which is independent of a specific in-lock detection. Hence, the results represent a useful tool for the design of an in-lock detector in PLL sweep systems.     

Current-Mode Phase-Locked Loops With CMOS Active Transformers

This paper introduces active transformer current- mode phase-locked loops (PLLs). The proposed PLLs replaces the RC loop filter of voltage-mode PLLs with an active transformer loop filter to take the advantage of their large inductance and small silicon area. A current-controlled LC oscillator with active inductors is employed to further reduce silicon area. The sensitivity of the cutoff frequency of active transformer loop filter to supply voltage fluctuation and process variation is analyzed. A 3-GHz PLL has been implemented in TSMC 0.18- $mu$m 6-metal 1.8-V CMOS technology and analyzed using SpectreRF with BSIM3v3 device models and Verilog-AMS from Cadence Design Systems. The lock time of the PLL is 60 ns. The power consumption and phase noise of the PLL are 16 mW and ${-}$100 dBc/Hz at 1-MHz frequency offset, respectively. The layout area of the PLL is 2800 $mu hbox{m}^2$.      

On the Pull-In Range of Phase-Locked Loops

The problem of determining the pull-in range of phaselocked loops is solved indirectly by evaluating the limit cycles of the loop in which the frequency error has a constant average. The analytical results derived here are in complete agreement with simulation results.     

Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise

Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and$bf 1/f$noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements.     

Phase-Controlled Apertures Using Heterodyne Optical Phase-Locked Loops

In this letter, we demonstrate the use of an electronic feedback scheme using a voltage controlled oscillator (VCO) to control the optical phase of individual semiconductor lasers (SCLs) phase locked to a common reference laser using heterodyne optical phase-locked loops (OPLLs). The outputs of two external cavity SCLs phase-locked to a common reference laser are coherently combined, and the variation in the relative optical path lengths of the combining beams is corrected by dynamically changing the phase of the offset radio-frequency signal fed into one of the OPLLs by means of a VCO. A stable power combination efficiency of 94% is achieved. This inherently different method of phase control, i.e., electronic rather than the use of electrooptic crystals, is deemed essential for new applications involving coherent optoelectronics.     

A Novel Calibration Method for Phase-Locked Loops

A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter to measure the natural frequency of the PLL; moreover it is capable of estimating the static phase offset. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.This work was carried out as a part of an internship at the QCT department of Qualcomm CDMA Technologies.Marco Cassia was born in Bergamo, Italy, 1974. He received the M.Sc. degree in engineering from the Technical University of Denmark, Lyngby, Denmark, in May 2000 and the M.Sc. degree in electrical engineering from Politecnico di Milano, Italy, in July 2000.From July 2001 to July 2002 he was with the QCT department of Qualcomm CDMA Technologies, San Diego, working in the field of direct modulation synthesizers. He is currently working toward the Ph.D.degree at the Technical University of Denmark.His main research interests are in the areas of low-power low-voltage RF systems.Peter Shah was born in Copenhagen Denmark in 1966. He completed his MScEE and Ph.D at The Technical University of Denmark in 1990 and 1993 respectively. From 1993 to 1995 he was a post doctoral research assistant at Imperial College in London, England, working on switched-current circuits. In 1996 he joined PCSI in San Diego (subsequently acquired by Conexant) as an RFIC design engineer, working on transceiver chips for the PHS cellular phone system. In 1998 he joined Qualcomm, also in San Diego, where he worked on RFICs for CDMA mobile phones and for GPS. In December 2002 he joined RFMagic where he is currently working on RFICs for consumer electronics. His research interests lie mainly in RFIC architecture and design, including sigma-delta PLLs and A/D and D/A converters, LNAs, mixers, and continuous-time filters.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I²L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ØrstedDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

Mathematical Analogies Between First-Order Digital and Analog Phase-Locked Loops

This concise paper provides an exact analysis of the phase error statistics of a first-order digital phase-locked loop (DPLL) by soloing the chapman-Kolmogorov equation using the method of moments. Both time independent and time dependent solutions are presented. In addition, the parameters which characterize the performance of a DPLL are identified with those of an analog phase-locked loop (APLL). It is Shown under what design parameter conditions the solution provided herein for a DPLL is equivalent to that obtained by applying the Fokker-Planck equation to the analysis of an APLL. Numerical comparisons are provided for specific parameter ranges of interest in practice.     

Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed.