一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply.     

一种单芯片无线收发系统设计

为了使无线收发系统能方便地应用于无线传感器网络、蓝牙技术与无限局域网（WLAN）等领域,采用了片上系统设计方法,将无线收发系统设计在一块单芯片上,使其最小化。给出了单芯片无线电的基本结构及电路实现的若干组成部分（混频器,低噪音放大器,功率放大器等）的解决方案。电路具有体积小,低功耗,成本低,可靠性高的特点。     

A Transceiver Front-End for Ultra-Wide-Band Applications

An integrated pulse based ultra-wide-band (UWB) transceiver front-end is presented in this paper. The pulse generator produces Gaussian modulated pulses satisfying Federal Communication Commission spectral mask with possibility for binary-phase shift keying modulation. The generated pulses have a bandwidth of 2 GHz from 3.1 to 5.1 GHz. The receiver front-end consists of an UWB low-noise amplifier (LNA). The transmit and receive paths are chosen by a transmit/receive (T/R) switch. The pulse generator, T/R switch and the LNA are integrated on a single chip and fabricated using 0.25-mum SiGe:C BiCMOS technology. The integrated circuit components are designed fully differential. The off-chip antenna and bandpass filter are single ended and connected to the T/R switch through a hybrid coupler     

锂离子电池的保护芯片设计

设计了一种基于CMOS工艺的锂离子电池保护芯片,采用工作在亚阈值区的电路结构,使电路具有高效低耗的特点,能够防止电池在工作过程中出现过充电、过放电、过电流和短路等异常状态。模拟结果表明,该芯片实现了基本保护功能并在功耗方面达到了设计目标。     

A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n)

802.11n is the latest offering from the IEEE standard committee tasked with enabling and enhancing WLAN systems. This standard utilizes several techniques to offer a much larger rate versus range than the legacy WLAN systems. A single-chip multiband direct-conversion CMOS MIMO transceiver (2times2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the draft 802.1 In standard and achieves PHY rates of > 270 Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40 dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8 V supply and with both cores operating, the chip draws 275 mA in RX mode and 280 mA in TX mode.     

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13-mum standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3-5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of -28 dB up to -4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer     

A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader

This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct I/Q up-conversion architecture. The frequency synthesizer based on a fractional-N phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 mum CMOS technology, and its die size is 4.5 mm times 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 mA apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dBm P1dB, an 18.5 dBm IIP3, and a maximum transmitter output power of 4 dBm.     

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

基于SOC的单芯片无线收发系统设计

在无线收发系统电路结构的基础上,分析了基于片上系统(SOC)的单芯片无线电通信最重要的收发部分的设计原理。给出了单芯片无线电的基本结构及电路实现的若干组成部分(混频器、低噪音放大器和功率放大器等)的解决方案。利用单芯片无线电体积小、低功耗、成本低和可靠性高的优点,在无线传感器网络、蓝牙技术与无限局域网(WLAN)方面具有广泛的应用。     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

Low-Power CMOS Rectifier Design for RFID Applications

We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas, coupled resonator impedance matching networks and low-power rectifiers in standard CMOS technologies (0.5-mum and 0.18-mum) and accurately predict their performance. Experimental results from a prototype power extraction system that operates around 950 MHz and integrates these components together are presented. Our measured RF power-up threshold (in 0.18-mum, at 1 muW load) was 6 muWplusmn10%, closely matching the predicted value of 5.2 muW.     

全球通用三频段GSM单芯片收发信机

本文所述是一个全球通用GSM单芯片收发信机的实现方式 ,介绍了基于GSM标准的多频段无线结构方框 ,讨论了此类结构方框实现全球通用GSM收发信机的可能性。该单芯片集成电路使用了0 5 μmBiCMOS工艺 ,并封装在一块“9× 9”的CABGA中。本文还介绍了该收发信机工作参数的测量结果。     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 μm by 171.8 μm with average power dissipation at 815.1 μW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 μm by 139.3 μm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 μm by 171.8 μm, was designed and implemented using TSMC 0.35 μm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.     

A CMOS Word Alignment Configurable Transceiver for Multi-Standard Fiber Communication Systems

This paper describes a configurable transceiver which can realize multiple operation modes to meet various fiber communication standards. With this configurable architecture, the transceiver can operate in 2：1, 3：1, 4：1, 5：1, 6：1, 8：1, 10：1 multiplexing modes and 1：2, 1：3, 1：4, 1：5, 1：6, 1：8, 1：10 demultiplexing modes with internal synchronized clock signals. Comma detection and word alignment circuits are also included in the receiver to meet the standards using 8B/10B code. This configurable multi-mode transceiver has been implemented in a 0.25μm CMOS technology.     

基于DMT的单片ADSL收发器

文章介绍了片上系统的设计方法,分析了一种非对称数字用户环路收发器片上系统芯片的组织结构、设计方法及设计难点,为今后开发具有知识产权的ADSL SOC芯片迈出了第一步。     

On the Transceiver Types of IR-UWB Systems at Sub-Nyquist Sampling Rates

In this paper, we present a unified performance analysis for different impulse radio (IR) ultra-wideband (UWB) transceiver types employing various modulation options and operating at sub-Nyquist sampling rates. Stored reference (SR), transmitted reference (TR), and energy detector (ED) receivers are considered employing one of the binary phase shift keying (BPSK), pulse position modulation (PPM), and on-off keying (OOK) modulation types. Realistic UWB channel models (the IEEE 802.15.4a channels) and practical pulse shapes (the root-raised cosine pulse) are used to characterize the statistics of the captured energies of different transceiver types at low sampling rates. The bit error rate (BER) expressions for different transceiver/modulation types are provided explicitly in additive white Gaussian noise channels. In multipath channels, the BER expressions are conditioned on the captured energies; then, the captured energy histograms at sub-Nyquist rates are used towards a semi-analytic evaluation of the BER for different transceiver/modulation combinations. The analyses are then verified via simulations using IEEE 802.15.4a channel models. The results show that in addition to their lower implementation complexities, the TR and ED receivers may be more favorable compared to SR receivers at low sampling rates in terms of their BER characteristics as well.