Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach.     

Bandwidth Enhancement for SSN Suppression Using a Spiral‐Shaped Power Island and a Modified EBG Structure for a λ/4 Open Stub

This paper proposes a spiral‐shaped power island structure that can effectively suppress simultaneous switching noise (SSN) when the power plane drives high‐speed integrated circuits in a small area. In addition, a new technique is presented which greatly improves the resonance peaks in a stopband by utilizing λ/4 open stubs on a conventional periodic electromagnetic bandgap (EBG) power plane. Both proposed structures are simulated numerically and experimentally verified using commercially available 3D electromagnetic field simulation software. The results demonstrate that they achieve better SSN suppression performance than conventional periodic EBG structures.     

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.     

一种基于互补环缝谐振器抑制SSN的新方法

针对高速PCB上抑制同步开关噪声(SSN)的问题,提出了一种将互补环缝谐振器(CSRR)刻蚀在电源平面上,抑制电源/地平面间的电场波动噪声传播的方法。采用基于有限元算法的HFSS软件对该结构进行仿真分析,结果表明:与理想参考平面和电磁带隙结构相比,刻蚀了该CSRR结构的电源分配网络具有较好的宽带全向SSN噪声抑制能力,在抑制深度为-40 dB时,其阻带覆盖从0.26 GHz到超过20 GHz以上的频率范围。     

Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.     

基于螺旋谐振环结构的UWB同步开关噪声抑制电源平面

针对目前印制电路板中采用的同步开关噪声抑制方法抑制带宽较窄、全向性较差、电源平面有效使用面积小、结构复杂及对信号质量影响大的问题,提出了一种基于螺旋谐振环结构的超宽带同步开关噪声抑制平面,具有结构简单、阻带宽、抑制方向具有全向性、无需周期性电磁带隙结构的特点。通过研究其等效电路模型,使用三维有限元法( FEM)对所设计的结构提取了S参数,并进行了频域与时域分析与仿真。仿真结果表明：所提出的结构其同步开关噪声抑制深度在-40 dB时,阻带范围为0.13~20 GHz,抑制带宽达到19.87 GHz,有效降低了带隙中心频率;当注入噪声电压为1 V时,可将噪声电压抑制到0.25 mV;对比UC-EBG和Planar EBG结构,在-40 dB抑制深度时,抑制带宽分别提高了16.97 GHz和17.73 GHz。     

PEEC结合有理缩减技术分析高速集成电路中同步开关噪声

利用部分元件等效电路 ( PEEC)方法分析高速集成电路系统中同步开关噪声 ,该方法相比其它等效电路方法及全波分析方法 ,具有简单、效率高 ,并可以和无源电路阶数缩减方法结合 ,进行大规模缩减 ,从而进一步提高计算速度。通过对电路中两种典型结构体 (电源 /接地板 ,电源板 /信号线 /接地板 )上同步开关噪声的分析 ,表明这种方法是分析高速集成电路中同步开关噪声的高效方法。     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.     

Efficient 2-D Integral Equation Approach for the Analysis of Power Bus Structures With Arbitrary Shape

A 2-D contour integral-equation method for the frequency-domain analysis of arbitrarily shaped power bus structures is presented. The numerically efficient approach allows the rapid and accurate computation of the frequency-dependent transfer parameters between an arbitrary number of ports, as required for embedding the power plane structure into network simulation. A formulation is developed for calculating the voltage distribution between the planes, as well as for determining the resulting radiated fields based on the field-equivalence principle. The method is applied for several test boards including a populated board with a surface-mount decoupling-capacitor network. The suggested approach is well confirmed by an analytical solution for the rectangular structure, by measurement and 3-D full-wave simulation results.      

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.     

A Double-Surface Electromagnetic Bandgap Structure With One Surface Embedded in Power Plane for Ultra-Wideband SSN Suppression

In this letter, a double-surface electromagnetic bandgap (EBG) structure with one EBG surface embedded in power plane is proposed for ultra-wideband simultaneous switching noise (SSN) suppression in printed circuit boards. The SSN suppression bandwidth is broadened to wider than 30 GHz with a low start frequency by combining traditional EBG structure and the coplanar EBG structure which is embedded in the power plane. Because the coplanar EBG surface is embedded in the power plane, no additional metal layer is introduced by the double-surface EBG structure. Simulations and measurements are performed to verify the broadband SSN suppression, high performance is observed.     

A simple finite-difference frequency-domain (FDFD) algorithm for analysis of switching noise in printed circuit boards and packages

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). Several methods have been used to investigate SSN. These methods ranged from simple lumped circuit models to full-wave (dynamic) three-dimensional Maxwell equations simulators. In this work, we present an efficient and simple finite-difference frequency-domain (FDFD) based algorithm that can simulate, with high accuracy, the capacity of a PCB board to introduce SSN. The FDFD code developed here also allows for simulation of real-world decoupling capacitors that are typically used to mitigate SSN effects at sub 1 GHz frequencies. Furthermore, the algorithm is capable of including lumped circuit elements having user-specified complex impedance. Numerical results are presented for several test boards and packages, with and without decoupling capacitors. Validation of the FDFD code is demonstrated through comparison with other algorithms and laboratory measurements.     

Direct computation of multiconductor transmission line capacitance and charge distribution

The per-unit-length capacitance parameter of multiconductor transmission line (MTL) is commonly extracted with indirect matrix transform method, which is complex and time-consuming. To solve the problem, an improved method to directly compute the MTL capacitance is proposed, which can be applied in the transmission line structure with arbitrary shaped cross-section and arbitrary separate distance. This method imports voltage conversions and matrix operations to simplify the complexity, improves computational efficiency by about 600% with results as accurate as previous method. The novel method presents a clear charge distribution map of MTL, whereas precious method will experience a tortuous process to get charge distribution.     

电磁带隙结构在同步开关噪声抑制中的应用分析

随着数字电路的噪声容限和时序容限不断减小,电源地平面上的同步开关噪声(SSN)成为高速设计的主要瓶颈之一.而现有抑制SSN的方法存在各自的不足,因而提出采用电磁带隙结构(EBG)设计来抑制SSN,软件仿真证明该方法是有效的.基于对多种不同结构EBG的研究,给出了EBG的设计思路和最新发展趋势,为今后的实际应用研究提供一定的参考与指导.     

Modeling of multilayered power distribution planes using transmission matrix method

This paper presents a method for analyzing multilayered rectangular and irregular shaped power distribution planes in the frequency and time domain. The analysis includes the effect of vias on the power distribution network. The planes are modeled using a two dimensional array of distributed RLCG circuit elements. Planes are connected in parallel using vias, which are modeled as self and mutual inductors. For the computation of the power distribution impedances at specific points in the network, a multiinput and multioutput transmission matrix method has been used. This is much faster than Spice and requires smaller memory. Using the transmission matrix method, via effects and the effects of multiple rectangular power/ground plane pairs without and with decoupling capacitors have been analyzed for realistic structures.     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

Partial uniplanar compact electromagnetic bandgap combined with high-impedance surface to suppress simultaneous switching noise

Proposed is a design for a partial uniplanar compact electromagnetic bandgap (UC-EBG) structure, in conjunction with a high-impedance surface (HIS), to suppress simultaneous switching noise (SSN) over the wide frequency range 0.38-15.494-GHz. Different from the conventional methods, which use an EBG plane, the proposed structure uses only two UC-EBGs at the excitation and receiving ports to suppress SSN. This technique can be applied to sensitive circuits to maintain their power integrity. The other region maintains good signal integrity when a signal return path is referenced to an EBG plane.     

A Power Plane With Wideband SSN Suppression Using a Multi-Via Electromagnetic Bandgap Structure

In this letter, a power plane with wideband simultaneous switching noise (SSN) suppression using a novel multi-via electromagnetic bandgap (EBG) structure is proposed. The -40dB stopband of the proposed EBG structure is about two to six times wider than the one-via structure, and the relative bandwidth is increased by about two times. It is implemented by only adding some vias between patches and the reference plane without changing any other geometrical parameters from one-via EBG structures. The excellent SSN suppression performance was verified by simulations and measurements     

系统级封装新型埋入式电源滤波结构的研究

在高密度小尺寸的系统级封装(SiP)中,对供电系统的完整性要求越来越高,多芯片共用一个电源网路所产生的电压抖动除了会影响到芯片的正常工作,还会通过供电网路干扰到临近电路和其他敏感电路,导致芯片误动作,以及信号完整性和其他电磁干扰问题.这种电压抖动所占频带相当宽,几百MHz到几个GHz的中频电源噪声普通方法很难去除.结合埋入式电容和电源分割方法的特点,提出一种新型高性能埋入式电源低通滤波结构直接替代电源/地平面.研究表明,在0.65～4GHz的频带内隔离深度可达-40～75 dB,电源阻抗均在0.25ohm以下,实现了宽频高隔离度的高性能滤波作用.分别用电磁场和广义传输线两种仿真器模拟,高频等效电路模型分析这种低通滤波器的工作原理以及结构对隔离性能的影响,并进行了实验验证.     

多导体传输线电感矩阵的直接算法

该文针对多导体电感矩阵通常需借助复杂间接方法求解的情况,提出一种多导体传输线电感矩阵的直接算法。利用双细线回路方程构建矩阵模型直接求解电感矩阵,降低了分析复杂度;并采用矩阵运算,在计算电感矩阵的同时求解多导体电流分布,解决了传统间接方法无法进行电流分析的难题。分析过程中采用非磁准近似条件和细线划分,可适用于宽频段、任意导体间距,任意横截结构情况。仿真结果表明,该算法在电感矩阵和电流分布的计算上均有较高精度。