对称三值电流型CMOS施密特电路

本文根据对称传输电流开关理论,设计了可具有多个输出的对称三值电流型CMOS施密特反相器。计算机模拟结果表明,它具有理想的施密特特性,并可根据需要调整回差。     

对称三值电流型CMOS施密特电路

本文根据对称传输电流开关理论，设计了可具有多个输出的对称三值电流型ＣＭＯＳ施密特反相器。计算机模拟结果表明，它具有理想的施密特特性，并可根据需要调整回差。     

基于开关信号理论的三值电流型CMOS电路设计

本文应用开关信号理论对电流型CMOS电路中MOS传输开关管与电流信号之间的相互作用进行了分析,并提出了适用于电流型CMOS电路的传输电流开关理论。应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能,从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。     

对称三值电流型CMOS电路设计

本文应用开关信号理论,建立了采用对称三值逻辑的传输电流开关理论,该理论能指导从开关级设计对称三值电流型CMOS电路.应用该理论设计的对称三值电流型CMOS电路不仅具有简单的电路结构和正确的逻辑功能,而且能处理具有双向特性的信号.     

基于控阈技术的电流型CMOS全加器的通用设计方法

利用电流信号的阈值易于控制这一特点,对电流型CMOS电路中如何实现阈值控制进行了研究.以开关信号理论为指导,建立了实现阈值控制电路的电流传输开关运算并具体指导设计了具有阈值控制功能的二值和多值电流型CMOS全加器.提出了适用于任意逻辑值的可控阈电流型CMOS全加器的通用设计方法.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了改善.最后给出了采用0.25μm CMOS工艺参数的HSPICE模拟结果及其能耗比较.     

三值TTL施密特电路的研究

本文通过对施密特电路的跳阈分析,指出在二值TTL施密特电路中实现该一功能的核心部件为阈值可控的差动电流开关。根据三值TTL电路有两个信号检测阈值的特点,本文设计了有二次跳阈反应的三值TTL施密特电路。PSPICE模拟证明了设计的电路具有理想的施密特电路功能。     

基于和图的三值电流型CMOS施密特反相器设计

基于阈算术代数系统理论,以和图为指导,分析施密特反相器的阈值可控开关,对三值电流型CMOS施密特反相器进行设计。Hspice仿真结果表明,该电路具有正确的逻辑功能和良好的瞬态特性,阈算术代数系统设计得到进一步的完善,三值施密特反相器设计更加简单直观。     

基于并联开关的低电压低功耗电流型CMOS电路设计

该文提出了一种电流型CMOS电路的并联开关结构,使得电流型CMOS电路能在较低的电源电压下工作,因而可以实现电路的低功耗设计,同时在相同的电源电压下,采用并联开关结构的电路比相应的串联开关电路具有更快的速度,PSPICE模拟证明了采用并联开关结构设计的电路能在较低的电源电压下工作,并具有较小的电路延时。     

一种新型低电压极限电流检测电路

为磁滞电流控制的DC-DC开关稳压器设计了一种新型的极限电流检测器。该电路不借助于专门的电流检测电路,只使用一个检测MOSFET和一个电压比较器来实现极限电流检测,减小了电路的复杂度。针对电流检测器的要求,设计了一种低电源电压、高共模电压的比较器。使用TSMC 0.18μm CMOS混合信号工艺,对电路进行设计。结果表明,电路具有很好的容差特性,并且电路可工作在1.2 V的低电源电压下。     

基于控阈技术的四值电流型CMOS电路设计

以开关信号理论为指导,对电流型CMOS电路中如何实现阈值控制进行了研究.建立了实现阈值控制电路的电流传输开关运算.在此基础上,设计了具有阈值控制功能的电流型CMOS四值比较器、全加器及锁存器等电路.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了优化.PSPICE模拟验证了所提出的电路具有正确的逻辑功能并且较之以往设计具有更好的瞬态特性和更低的功耗.     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger circuit has been realised, using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.     

A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis

This paper presents a brief overview of Schmitt triggers and proposes a new differential current-feedback Schmitt trigger. The hysteresis of the proposed Schmitt trigger is generated using regenerative current feedback and can be adjusted by varying the current of the regenerative feedback network. The center of the hysteresis can also be adjusted by varying the common-mode input voltage. The proposed Schmitt trigger has the characteristics of current-mode circuits, making it particularly attractive for low-voltage high-speed applications. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.     

Design techniques for ASK demodulators of passive wireless microsystems: a state-of-the-art review

This paper presents a brief overview of Schmitt triggers and proposes a new differential current-feedback Schmitt trigger. The hysteresis of the proposed Schmitt trigger is generated using regenerative current feedback and can be adjusted by varying the current of the regenerative feedback network. The center of the hysteresis can also be adjusted by varying the common-mode input voltage. The proposed Schmitt trigger has the characteristics of current-mode circuits, making it particularly attractive for low-voltage high-speed applications. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.     

CMOS current Schmitt trigger with fully adjustable hysteresis

A CMOS current Schmitt trigger whose hysteresis is independent of process parameters, transistor dimensions and power supplies is described. The hysteresis is determined by two currents and is adjustable over the range of the input current. The circuit function can be extended to a two-input current comparator with adjustable hysteresis.<>     

Novel CMOS Schmitt trigger with controllable hysteresis

A novel CMOS Schmitt trigger with controllable hysteresis based on the standard CMOS circuit with three transistor pairs is proposed. With the addition of only one transistor pair a Schmitt trigger with two selectable hysteresis characteristics can be achieved. Simulation results are compared with theory and a possible application is presented.<>     

A new waveform-reshaping circuit: an alternative approach toSchmitt trigger

A waveform-reshaping circuit that is conceived as an alternative to the conventional Schmitt trigger is introduced. This circuit employs ratioless inverters, which require no standby current and are for high-speed operations. Two different logic threshold voltages of the CMOS inverters in the circuit determine the hysteresis characteristics     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.     

Low-voltage high-speed Schmitt trigger and compact window comparator

Gates with input hysteresis are often necessary in circuits operating in noisy environments. Described is a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications. The circuit also allows the construction of a very compact window comparator.     

Low power Schmitt trigger circuit

Three new Schmitt trigger circuits are described. The first circuit is a truly low power, while the second and third circuits are derived from the first circuit and provide smaller hysteresis width. Measurement results for the new Schmitt trigger circuits are presented. All the designed circuits are simulated using HSPICE with level 28 model parameters for a 1.2 μm standard CMOS technology. An application to the design of low power, very low frequency integrator oscillators is described