Precise 90/spl deg/ quadrature current-controlled oscillator tunable between 50-130 MHz

A VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8 /spl mu/m CMOS process is presented. The oscillator is tunable in the frequency range from 50-130 MHz. The two phases produced by the oscillator show an extremely low phase difference error (less than 2/spl deg/ over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.     

High frequency current mode oscillator employing fTintegration technique

A low distortion high frequency oscillator is described, which is a development of the recently proposed f_T-integrator, in which an amplitude control circuit is embedded inside the integrator. Simulation results suggest that, for the oscillation range 1-2.6 GHz, the total harmonic distortion (THD) of the output current signal is well below 0.5% for the output current level at 50% modulation depth (peak-to-peak). The phase noise of the oscillator is simulated to be -72 dBc/Hz at 1 MHz offset for 1% THD output current     

A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-$mu rm g$ Bias Stability and 20-$ murm g/sqrt{{hbox{Hz}}}$ Resolution

A fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 mug/radicHz resolution and 4 mug bias stability. The readout circuit draws 7 mA under 3.3-V supply.     

A universal 0.03-mm2 one-pin crystal oscillator in CMOS

A one-pin crystal oscillator with an integrated load capacitance of 15 pF has been realized in a standard 0.35-μm CMOS technology. Due to the structure of the oscillator and the use of MOS gate capacitance for the load capacitors, the chip area can be very small. The total active area including load capacitors is less than 0.03 mm². The design can be operated with supply voltages in the range of 1.4-3.6 V and allows crystal frequencies in the range of 3-30 MHz. The current consumption of the oscillator core is 180 μA at 10 MHz with 3.3-V power supply. It produces a rail-to-rail output swing, regulated by an amplitude control loop, and has the same flexibility and ease of frequency tuning as a common Pierce oscillator. As no special IC process options are required, the design is very suitable for clock generation in digital very-large-scale-integration chips     

Designer's Casebook-compact detector stabilized LCoscillators

An averaging or peak-voltage detector is generally incorporated in an RC oscillator for stabilizing its amplitude. Corresponding circuitry for an LC oscillator, however, is usually cumbersome because it requires two LC circuits tuned to the same frequency. An amplifying circuit that operates as a linear current divider for LC oscillators to overcome this problem is presented     

用于315/433MHz超再生接收机的射频前端关键技术

采用0.5μm CMOS工艺实现了用于315/433MHz超再生无线接收机的射频前端电路,包括射频放大器和超再生振荡器。文中提出了一种改进型有源电感,提高了射频放大器中谐振回路的品质因数。阐述了振荡器的自偏置效应以及振荡器输出信号幅度和电流源的关系,在此基础上实现了适用于包络检波的差分结构超再生振荡器。测试结果显示,电源电压范围为2.5V~5V,电流小于2.5mA,系统接收灵敏度优于-90dBm。     

A Wien bridge RC oscillator with fast amplitude control

The paper describes fast amplitude control in a Wien bridge RC oscillator. This fast control is achieved restoring ( within each period) a node voltage in the passive RC two-port of positive feedback. As a result the new value of the output voltage amplitude can be established with the delay which is not more than one oscillation period. The total harmonic distortion ( THD) is calculated and the condition of low distortion is established. The low-THD oscillator includes the circuit for damping-ratio control as well. The experimental data show that THD below 0-1% is achieved.     

A Single Chip 160 Mbit/s Cable Communication Circuit Including a Gain Controlled Equalizer and a Data Regenerating PFLL

In this paper a single chip transmitter and receiver interface circuit for 160 Mbit/s CMI-coded data transmission is presented. The receiver circuit includes a 12 dB cable equalizer to compensate for nonconstant cable attenuations. There is also a PFLL for data regeneration and to extract a 320 MHz oscillator clock signal. The frequency characteristics of the equalizer are controlled with an automatic gain control loop (AGC). The PFLL is a combination of two separate control loops, the purpose of which is to keep the integrated oscillator on the narrow locking range of the data loop. The frequency loop has been designed with a frequency detector to avoid interferences between the two control loops. The transmitter includes a cable driver supplying a stable 1 Vpp signal amplitude to the transmission line and also a PLL to extract a 320 MHz clock signal.     

Current amplitude control circuits suitable for current-modeoscillators

A novel current amplitude control circuit suitable for current-mode oscillators is proposed. The circuit is a modified version of the well-known Gilbert gain cell. The technique obtains independent control of oscillation amplitude and small-signal current gain. As an example, the amplitude control circuit is applied to a current-mode oscillator. Simulations were carried out using HSPICE with 0.8 μm Nortel BiCMOS technology and Motorola RF transistors. Simulated results demonstrate that the nonlinear current gain control circuit behaves in a well defined manner. Low distortion and high frequency oscillations are easily obtained when the circuit is applied to a current-mode oscillator     

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO withwide-band low-noise automatic amplitude control loop

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 μA are drawn by the AAC circuit     

Sliding-Mode Amplitude Control Techniques for Harmonic Oscillators

This paper investigates both theoretical and implementation-level aspects of switching-feedback control strategies for the development of harmonic oscillators. We use sliding-mode compensation based on various norms of the system state to achieve amplitude control over a wide-tuning range. A 7.6-MHz I/Q LC oscillator is developed and tested. Measurements show that implementation of the proposed switch-based amplitude controller provides accurate amplitude control over the entire frequency tuning range while inducing only a minor phase noise degradation (of less than 2 dBc/Hz).     

A compact full MMIC module for Ku-band phase-lockedoscillators

A compact Ku-band phase-locked oscillator module has been developed in a full MMIC (monolithic microwave integrated circuit) configuration. The module includes an MMIC voltage-controlled oscillator, an analog frequency divider, and interstage amplifiers. The constituent monolithic chips are integrated in a very small single-package module and operate at the target frequencies without any external trimming or matching network. The oscillator is tuned more than 1 GHz with a constant output amplitude. The frequency-divided output is also obtained over the whole tuning range. Spurious output is not found at any frequency up to 22 GHz. In spite of the very low-Q factor of GaAs monolithic circuitry, the oscillator phase noise exhibited is less than -80 dBc/Hz, due to the high-gain, high-speed phase lock     

Finding the Tuning Curve of a CMOS—LC VCO

A nonlinear perturbation model of a complementary LC-tuned voltage-controlled oscillator is derived, which consists of two mutually-coupled second-order differential equations. The first-order approximate periodic solution of the describing equations is found, obtaining closed-form expressions for both the amplitude and the harmonics of oscillation, as well as for the correction of the oscillation frequency due to the nonlinear effect of varactors. This allows us to find the tuning curve in explicit form. The accuracy of presented formulas was validated by circuit simulations.      

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

具有自动增益控制的射频振荡器稳定性分析

设计了一个具有自动增益控制(AGC)的电路来稳定射频功率振荡器的输出幅度,然而在加入AGC负反馈环路之后,该环路可能会产生自激振荡,使得振荡器输出的幅度更加不稳定。通过对整个电路系统传递函数的分析,采用调节反馈电路中三极管发射极电阻阻值的方法,使该电路工作在稳定的状态,进而达到稳定振荡器输出幅度的目的。     

A 5 GHz, 192.6 dBc/Hz/mW FOM, LC–VCO System With Amplitude Control Loop and LDO Voltage Regulator in 0.18 μm CMOS

To reduce phase noise degradation from oscillator tail current sources, this letter presents an inductor-capacitor voltage-controlled oscillator (LC-VCO) biased by triode metal-oxide-semiconductor transistors. The VCO system also includes an amplitude control loop and a voltage regulator to endure process, voltage, and temperature variations and to enhance power supply rejection ratio. Fabricated in a 0.18 mum CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source. At 5.181 GHz, the VCO system demonstrates a phase noise of -104.8 dBc/Hz at 100-kHz offset, and -127.1 dBc/Hz at 1 MHz offset, while dissipating 4.2 mA from a 1.8 V supply voltage. The corresponding figures of merit at 100 kHz and 1 MHz offset are 190.3 and 192.6 dBc/Hz/mW, respectively.     

Cascadable Current-Mode Biquad Filter and Quadrature Oscillator Using DO-CCCIIs and OTA

This article introduces a circuit which can function both as a quadrature oscillator and as a universal biquad filter (lowpass, highpass, bandpass). When the circuit functions as a universal biquad filter, the quality factor and pole frequency can be tuned orthogonally via the input bias currents. When it functions as a quadrature oscillator, the oscillation condition and oscillation frequency can be adjusted independently by the input bias currents. The proposed circuit can work as either a quadrature oscillator or a biquad filter without changing the circuit topology. The amplitude of the proposed oscillator can be independently controlled via the input bias currents. The proposed oscillator can be applied to provide amplitude modulated/amplitude shift keyed signals with the above-mentioned major advantages. The circuit is very simple, consisting of four dual-output second generation current controlled current conveyors (DO-CCCIIs), one operational transconductance amplifier (OTA), and two grounded capacitors. Without any external resistors and using only grounded elements, this circuit is therefore suitable for IC architecture. PSPICE simulation results are depicted here, and the given results agree well with the theoretical analysis. The power consumption is approximately 7.32 mW at ±2.5 V supply voltages.     

Amplitude Stabilized Transistorized Low Frequency Oscillator†

While generating very low frequency sinusoidal voltage, using operational amplifiers, one experiences difficulties in stabilizing the amplitude and every endeavour has been made to get a satisfactory solution. The paper describes one method by which stable oscillation can be obtained to a frequency as low as 0·01 c/s. The oscillator consists of two integrators and one sign changer interconnected in the form of a closed loop so as to solve a second-order differential equation. The amplitude is stabilized with the help of an extra stabilizing loop which consists of a squaring network. A brief analysis of the oscillator has been carried out and the precautions that have to be taken for improving the oscillator performance are discussed     

开关电容振荡器的起振和幅值稳定的研究

本文讨论了开关电容振荡器(SCO)的起振和幅值稳定问题。提出了SCO的起振和幅值稳定的新方法。给出了稳定性好的幅值控制电路。在多相SCO的设计中,幅值控制电路的复杂程度不随振荡器的相数增加而增加。实验结果与理论相符。     

DC instability of the series connection of tunneling diodes

An oscillator with a series connection of tunneling diodes produces significantly higher power than a single diode oscillator. However, a circuit with series-connected tunneling diodes biased simultaneously in the negative differential resistance (NDR) region of the I-V curve is dc unstable. This dc instability makes the series connection oscillator fundamentally different from a single diode oscillator. Associated with the dc instability are the phenomena of minimum oscillation amplitude and frequency. Due to the minimum oscillation amplitude, it is critical to provide the impedance match between the oscillator circuit and the series connection at the desired oscillation amplitude level. An in depth, comprehensive analysis of the dc instability is given here. Based on this analysis, a numerical procedure is developed to accurately predict the minimum oscillation amplitude and frequency. Time domain simulations which give further insight into series-connection oscillator behavior are discussed. The effect of increasing the number of diodes on the oscillator performance is explored as well. Based on numerical and simulation results, oscillators with several tunnel diodes connected in series were designed and tested. Experimental results that confirm the existence of the minimum oscillation amplitude are presented for oscillators with two, three, and four tunnel diodes