Degradation of d.c. parameters in enhancement mode WNx self-aligned gate GaAs MESFETs under high temperature stress

The effect of thermal stress on the d.c. parameter degradation of enhancement mode tungsten nitride (WN_x) self-aligned gate GaAs MESFETs was investigated. Threshold voltage, source-drain current and transconductance were measured during the tests. The physical properties of the device after thermal stress were analyzed by means of Auger electron spectroscopy (AES), X-ray diffractometry to identify the degradation mechanism. The d.c. failure mode consists of an increase in the threshold voltage and a decrease in the current and transconductance of the FETs. The device simulator was also used for analytical understanding of the d.c. parameter degradation. The simulated results showed that d.c. parameter degradation was mainly attributed to the increase in source and drain ohmic contact resistances. From the AES analysis, we found that the increase of contact resistance was due to carrier compensation, which was caused by Ga outdiffusion and Ni indiffusion under the ohmic contact layer. Therefore the thermally activated carrier compensation effects by trap generation are proposed to be the main failure mechanism for d.c. parameter degradation of enhancement mode WN_x self-aligned gate GaAs MESFETs.     

Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Bias-temperature stress examinations of self-aligned 0.1 μm length gate GaAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower doping concentration, the increase in threshold voltage in FETs was faster and a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200°C. The recovery of the performance under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration and thus we obtained the prediction of a median life exceeding 10⁶ h at 100°C by setting the Si dose of 4 × 10¹³ cm⁻², which is as high as it can be set without causing serious reduction of breakdown voltage.     

The effects of buffer thickness on GaAs MESFET characteristics: channel–substrate current, drain breakdown, and reliability

The effects of thickness in metal–semiconductor field effect transistor (MESFET) GaAs buffer on the device electrical performance and reliability have been investigated. Devices studied are 0.8-μm-gate GaAs MESFETs at different buffer thickness of 0.5 and 0.3 μm from similar MBE-grown processes. Three-terminal off-state breakdown measurements indicate that a substantial enhancement in the observed breakdown current for thinner-buffer MESFETs is attributed to the drain–source leakage or breakdown through the channel–substrate interface while the device is at pinch-off. DC and RF biased stress lifetests up to 323 °C channel temperature have been performed to accelerate the degradation mechanisms. It is found that the device degradation rate has little dependence on buffer thickness when stressed at a reversed gate–drain voltage below 70% of its breakdown threshold. The differences grow rapidly when biased close to the breakdown field because of the development of channel–substrate current in thinner buffer materials.     

DC and pulsed measurements of on-state breakdown voltage in GaAs MESFETs and InP-based HEMTs

The BV_DS–I_D breakdown characteristics of MESFET and HEMT devices measured at constant gate current are correlated with conventional measurements of gate current due to impact-ionization. The influence of thermal effects on breakdown DC measurements is demonstrated. By adopting pulsed measurements, we confirm that on-state breakdown voltage of InP HEMTs decreases by increasing the temperature, while the opposite occurs in GaAs based MESFETs and HEMTs. We show that DC measurements are not suitable for evaluating on-state breakdown of power MESFETs and HEMTs, and we propose pulsed measurements as a viable alternative.     

TiA1和TiPtAu栅GaAs MESFET稳定性研究

在高温和大栅电流下 ,对 Ti Al栅和 Ti Pt Au栅 MESFET的稳定性进行了比较研究 ,结果表明 :( 1)两种器件的击穿电压稳定 ,栅 Schottky接触二极管理想因子 n变化不明显 ;( 2 ) Ti Al栅的 MESFET的栅特性参数 (栅电阻 Rg,势垒高度 Φb)变化明显 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 等 )保持相对不变 ;( 3)对 Ti Pt Au栅MESFET来说 ,栅 Schottky二极管特性 (栅电阻 Rg,势垒高度 Φb)保持相对稳定 ,与沟道特性相关的器件参数 (如最大饱和漏电流 Idss,栅下沟道开路电阻 R0 ,夹断电压 Vp0 、跨导 gm 等 )明显变化 ,适当退火后 ,有稳定的趋势。这两种器件的参数变化形成了鲜明的对比。     

Stationary charge domain in GaAs MESFETs: dimensional and electrical characterisation

Numerical results of the location, size and voltage associated with stationary dipole charge layers in GaAs MESFETs and their dependences on gate and drain bias are presented. The results suggest the need of more analytical work describing the domain characteristics for a better understanding of how the dipole charge layer influences GaAs MESFET operation.<>     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Thermally induced parasitic ungated FET in power MESFETs

The onset of a parasitic FET between the gate and the source (drain) has been observed by monitoring the reverse gate diode I−V characteristics of power GaAs MESFETs, subjected to accelerated aging tests. Such anomalous characteristics are attributed to localized microreactions at the gate metal-GaAs interface, which can be preferential sites for the occurrence of burn-out phenomena.     

High-transconductance enhancement-mode GaAs MESFET fabrication technology

An improved enhancement-mode GaAs MESFET was fabricated by a high dose Si ion implantation which was used to reduce the source and drain parasitic resistances, and by a Pt buried gate which was used to control the threshold voltage and reduce the interface states of the Schottky gate. 250 mS/mm transconductance has been obtained for 1-µm gate-length enhancement-mode GaAs MESFET.     

Characterisation and modelling of parasitic effects and failure mechanisms in AlGaN/GaN HEMTs

This work is a study of the degradations of AlGaN/GaN HEMTs induced by 2000 h of ageing tests. The methodology is based on cross-characterisation analysis.The life tests (HTO 150 °C, HTO 175 °C and HTRB 175 °C and Idq 90 °C) have mainly induced a decrease of the saturation drain current, occurring during the first 50 h, followed by a stabilisation. There is a shift of the pinch-off voltage in the range of 0.1–0.2 V while the Schottky contact is rather stable after ageing. The evolution of the electrical characteristics after ageing does not depend on the bias conditions but rather more on the channel temperature. It seems to be neither field nor current driven. Low frequency drain current noise demonstrates that there is no trap creation and the weak evolution of the 1/f noise confirms that there is no degradation in the channel. Moreover, pulsed I–V measurements show a weak evolution of gate lag and drain lag rates after ageing. The same degradation mode is demonstrated for all life tests with rather high activation energy of 1.6 eV. The weak evolution of electrical characteristics observed during the life tests cannot be obviously explained by a single physical mechanism and results from a combination of trap-related effects before stabilisation.     

High-breakdown-voltage MESFET with a low-temperature-grown GaAspassivation layer and overlapping gate structure

GaAs MESFETs were fabricated using a low-temperature-grown (LTG) high-resistivity GaAs layer to passivate the doped channel between the gate and source and between the gate and the drain. The gate was fabricated such that the source and drain edges of the metal gate overlapped the LTG GaAs passivation layer. The electric fields at the edges of the gate were reduced by this special combination of LTG GaAs passivation and gate geometry, resulting in a gate-drain breakdown voltage of 42 V. This value is over 60% higher than that of similar MESFETs fabricated without the gate overlap     

Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

An improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region was proposed. The recessed source/drain drift region is to reduce channel thickness between gate and drain as well as eliminate gate depletion layer extension to source/drain. The recessed source/drain drift region of the proposed structure can be realized with the formation of double-recessed gate region. The simulated results showed that the breakdown voltage of the proposed structure is 145 V compared to 109 V of that of the published 4H-SiC MESFETs with double-recessed gate structure and yet maintain almost same saturation drain current characteristics. The output power density of the proposed structure is about 33% larger than that of the published double-recessed gate structure. The cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of the proposed structure are 21.8 GHz and 81.5 GHz compared to 19.0 GHz and 76.4 GHz of that of the published double-recessed gate structure, respectively.     

Degradation mechanism of GaAs MESFETs

The reliability of the Au/Pt/Ti Schottky gate of low-high doped GaAs MESFETs has been investigated by thermal step stress and accelerated life tests and their degradation mechanisms were analyzed by means of Auger electron spectroscopy, X-ray diffractometry, cross-sectional transmission electron microscopy, current-voltage, and capacitance-voltage measurements. Electrical measurements showed that the failure of the GaAs MESFETs was mainly due to the degradation of the Au/Pt/Ti/GaAs Schottky contact. An activation energy of 1.3 eV and a lifetime of 2 × 10⁸ h at 125°C for Schottky contact were evaluated. At a temperature lower than 350°C, the degradation of the Schottky contact is attributed to the decrease of net electron concentration caused by outdiffusion of host Ga atoms of GaAs. The activation energy for the decrease of net electron concentration is determined to be 1.4 eV using the capacitance-voltage measurement, which is consistent with 1.3 eV obtained by the accelerated life tests. This suggests that the major thermal degradation mechanism at a temperature lower than 350°C is the outdiffusion of Ga atoms from the channel. Meanwhile, the effective channel thickness at a temperature higher than 350°C is reduced by the formation of TiAs at the Schottky interface, the activation energy of which is determined to be 1.74 eV.     

Breakdown of overlapping-gate GaAs MESFETs

Gate-breakdown mechanisms in GaAs MESFETs have been studied by numerical simulation. The devices simulated include normal passivated and unpassivated MESFETs as well as overlapping-gate MESFETs passivated with low-temperature-grown (LTG) GaAs, normal GaAs, and silicon dioxide. The breakdown voltage is the highest for the overlapping-gate MESFET with LTG GaAs passivation, which agrees with the experimental results reported previously. The high breakdown voltage is the result of an altered electric field near the drain-edge of the Schottky-contact gate. This field modification is achieved most effectively by using an overlapping gate structure. The LTG GaAs is the best passivation layer because of its high resistivity and breakdown-field strength     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

High performance GaAs MESFETs with molecular implanted and optimized lowly-doped drain structure for maximized speed, gain and breakdown performance

GaAs MESFETs with novel lowly-doped drain structures have been developed utilizing molecular implants of silicon trifluoride. Short-channel effects in the 1/4 μm enhancement- and depletion-mode transistors have been suppressed with drain-induced barrier height lowering of less than 70 mV/V and pinch-off voltage shifts of less than 220 mV as the gate length was scaled from 1.0 to 1/4 μm. The 3-terminal breakdown, the transconductance to output conductance ratio, and the unity current gain, cut-off frequency were simultaneously optimized. The E-mode device possessed breakdown of >10 V, G_m · R_ds > 9.5, F_t > 55 GHz, and nominal on-resistance of 2.1 Ω mm while the D-mode device had breakdown >10 V, G_m · R_ds > 6.0, F_t > 45 GHz, and nominal on-resistance of 1.9 Ω mm. These optimized transistors enabled the realization of a variety of low-power digital and high-power mixed signal circuits, using 3-level source-coupled transistor and common-mode logic, such as laser and electro-optic drivers, highly integrated transceivers, multiplexers, demultiplexers, and clock data recover circuits.     

Millimeter-wave ion-implanted gradedInxGa1-xAs MESFETs grown by MOCVD

The authors present the fabrication and characterization of ion-implanted graded In_xGa_1-xAs/GaAs MESFETs. The In_xGa_1-xAs layers are grown on GaAs substrates by MOCVD (metal-organic chemical vapor deposition) with InAs concentration graded from 15% at the substrate to 0% at the surface. 0.5-μm gate MESFETs are fabricated on these wafers using silicon ion implantation. In addition to improved Schottky contact, the graded In_xGa _1-xAs MESFET achieves maximum extrinsic transconductance of 460 mS/mm and a current-gain cutoff frequency f_t of 61 GHz, which is the highest ever reported for a 0.5-μm gate MESFET. In comparison, In_0.1Ga_0.9As MESFETs fabricated with the same processing technique show an f_t of 55 GHz     

Characterization of SiC MESFETs with narrow channel layer

SiC MESFETs with a narrow channel layer are proposed to alleviate the short-channel effects, in particular the drain-induced barrier lowering (DIBL) effect that results in threshold voltage that is dependent on the gate length and the drain voltage applied. Such narrow channel layer 4H-SiC MESFETs were fabricated and characterized. The thickness and doping concentration of the channel layer are 0.08 μm and 8.0 × 10¹⁷ cm⁻³, respectively. The measurement results showed that the threshold voltage of the MESFETs is about −1.1 V and is independent of the gate length from 1 to 3 μm, and the drain voltage applied up to 40 V. Good saturation behavior with fairly low output conductance was also achieved, which is desirable for small signal applications. The results obtained for the narrow channel layer MESFETs are also compared with those measured for conventional devices with thicker channel layer of 0.20 μm and doping concentration of 2.5 × 10¹⁷ cm⁻³.     

Thermal stability of Al/Ni gate AlGaAs/GaAs HEMT's

The study on the instability of gate contacts of Al/Ni gate AlGaAs/GaAs HEMT's was performed by means of storage tests carried out at three different temperatures: 200°C, 240°C and 300°C. Data from tests as long as 5000 hours were analyzed. At the highest temperature the main failure mode was the reaction between the Al of the gate electrode and the Au of the metallization. At 200°C, 240°C an increase of the barrier height was detected. The activation energy determined and the comparison with the data existing in literature is reported.