Degradation of d.c. parameters in enhancement mode WNx self-aligned gate GaAs MESFETs under high temperature stress

The effect of thermal stress on the d.c. parameter degradation of enhancement mode tungsten nitride (WN_x) self-aligned gate GaAs MESFETs was investigated. Threshold voltage, source-drain current and transconductance were measured during the tests. The physical properties of the device after thermal stress were analyzed by means of Auger electron spectroscopy (AES), X-ray diffractometry to identify the degradation mechanism. The d.c. failure mode consists of an increase in the threshold voltage and a decrease in the current and transconductance of the FETs. The device simulator was also used for analytical understanding of the d.c. parameter degradation. The simulated results showed that d.c. parameter degradation was mainly attributed to the increase in source and drain ohmic contact resistances. From the AES analysis, we found that the increase of contact resistance was due to carrier compensation, which was caused by Ga outdiffusion and Ni indiffusion under the ohmic contact layer. Therefore the thermally activated carrier compensation effects by trap generation are proposed to be the main failure mechanism for d.c. parameter degradation of enhancement mode WN_x self-aligned gate GaAs MESFETs.     

On the temperature variation of threshold voltage of GaAs MESFETs

The authors have investigated the temperature dependence of the threshold voltage of depletion-mode GaAs MESFETs with epitaxially grown n channels. An approach to threshold shift analysis that allows direct comparison with threshold measurement is taken. The contributions from various temperature-dependent effects to the threshold-voltage shift were studied, including the built-in voltage of the Schottky barrier, deep-level transients, capping layer effects, the substrate-channel built-in voltage, and the k factor which is related to channel mobility. A quasi-DC method for threshold voltage measurement, which enables threshold voltage to be measured as a function of temperature with minimum deep-level transient effect is reported. A method has also been developed to measure the temperature dependence of built-in voltage which is completely free from transient effects. The results show that the major contributors to the temperature variation of threshold voltage are the temperature dependence of the Schottky barrier built-in voltage and the effect of the capping layer     

New high power planar gate GaAs MESFETs with improved gate-drainbreakdown voltage

The authors present a new approach to power GaAs MESFETs with planar gate structures, based on the MBE growth technique on an undoped surface GaAs layer on an ion-implanted channel layer. This undoped GaAs layer increases the gate-drain breakdown voltage and serves as both an ideal passivation layer and an ideal annealing cap of ion implanted channels. To realise a good surface condition before MBE growth, the UV-ozone surface treatment is introduced. This new simple structure offers high performance power GaAs MESFETs     

Uniformity of threshold voltage for MESFETs fabricated on VGF GaAs substrates

Improved uniformity of threshold voltage is shown for MESFETs fabricated on GaAs substrates grown by a novel vertical gradient freeze technique when compared to devices fabricated on LEC GaAs substrates. The improved uniformity is most likely related to the decreased dislocation density and reduced impurity clustering in the VGF material.     

Modeling of the gate junction in GaAs MESFETs

A low-signal equivalent circuit of a GaAs MESFET is suggested. In this circuit, the gate junction is represented so that a potential variation along the channel can be taken into account. A relationship between the gate current and the gate-source and drain-source voltages is found     

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiNx gate insulator for high hole mobility

In this work, the GaN p-MISFET with LPCVD-SiN_x is studied as a gate dielectric to improve device performance. By changing the Si/N stoichiometry of SiN_x, it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN_x gate dielectric, which leads to a respectably improved drive current of GaN p-FET. The record high channel mobility of 19.4 cm²/(V·s) was achieved in the device featuring an Enhancement-mode channel. Benefiting fr...     

Use of pt gate metallization to reduce gate leakage current in GaAs MESFETs

The use of wet-chemical removal of native oxide in a sealed nitrogen ambient prior to deposition of metal on GaAs is shown to be an effective method of engineering the Schottky barrier height of the metal contacts. Due to its higher metal work function, a barrier height of 0.98 eV for Pt on n-type GaAs is demonstrated. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV). MES-FETs fabricated using PtAu bilayer contacts show reverse currents an order of magnitude lower than TiPtAu contacted companion devices, higher reverse breakdown voltages and much lower gate leakage. Utilizing this technology of oxide removal and the PtAu bilayer contact provides a much simpler method of enhancing the barrier height on re-type GaAs than other techniques such as counter-doping the near-surface or inserting an interfacial layer.     

Numerical analysis of the gate voltage dependence of the seriesresistances and effective channel length in submicrometer GaAs MESFETs

A detailed numerical analysis of the source and drain parasitic resistances and effective channel length of state-of-the-art GaAs MESFETs is presented. Two-dimensional simulations are used to evaluate different criteria (physical and electrical) for defining the device parameters of interest, as well as to study their gate voltage dependence. To this purpose a novel criterion which provides a simple procedure to determine the series resistances as a function of gate bias is proposed     

Current—voltage characteristics of an AlGaAs/GaAs heterostructure FET for high gate voltages

Drain-to-source current for high gate voltages in AlGaAs/GaAs heterostructure FET's (HFET's) is found to depend on the electron saturation velocity in the AlGaAs layer. A simple model, which takes into account the current through the undepleted channel in the AlGaAs layer as a function of the electron saturation velocity in AlGaAs, is proposed for describing I-V characteristics of HFET's for high gate voltages. Using the model, effective electron saturation velocity in AlxGa1-xAs for different Al content levels has been obtained from the analysis of the present experimental results; 7 × 10⁶cm/s for x = 0.24 and 3 × 10⁶cm/s for x = 0.3 at a 4 × 10¹⁷cm^-3doping concentration.     

Applications of single and dual gate GaAs MESFETs for Gbit/s optical data transfer systems

Intrinsic large signal rise and fall times of less than 30 ps without charge storage demonstrate the potential of single and dual gate GaAs MESFETs for Gbit/s optical communication systems. The applications as signal regenerator, bit synchronizer, laser modulator, multiplexer, and demultiplexer are shown. Using only one dual gate GaAs MESFET clock and pulse shape regeneration as well as 1 Gbit/s laser modulation is performed. Bit synchronization is demonstrated up to 4 Gbit/s. 1 to 2 Gbit/s and 2 to 4 Gbit/s multiplexing as well as 2 to 1 Gbit/s demultiplexing with additional clock and pulse shape regeneration is shown using dual gate FETs. 2 to 4 Gbit/s multiplexing without clock regeneration is also accomplished using single gate GaAs MESFETs.     

Mechanisms of temperature dependence of threshold voltage in high-k/metal gate transistors with different TiN thicknesses

The change in temperature coefficient of the threshold voltage (=dV_th/dT) for poly-Si/TiN/high-k gate insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) was systematically investigated with respect to various TiN thicknesses for both n- and p-channel MOSFETs. With increasing TiN thickness, dV_th/dT shifts towards negative values for both n- and p-MOSFETs. A mechanism that changes dV_th/dT, depending on TiN thickness is proposed. The main origins are the work function of TiN (Φ_TiN) and its temperature coefficient (dΦ_TiN/dT). These are revealed to change when decreasing the thickness of the TiN layer, because the crystallinity of the TiN layer is degraded for thinner films, which was confirmed by ultraviolet photoelectron spectroscopy (UPS), transmission electron microscopy (TEM) and X-ray diffraction (XRD).     

A high threshold voltage uniformity MIS-like heterostructure FET using n+-Ge as a gate electrode

A new n+-Ge/ undoped-AlxGa1-xAs/ undoped-GaAs MISlike heterostructure FET (n+-Ge-HFET), using n+-Ge layer as a gate electrode material, is shown to have a high threshold voltage uniformity (sigmaV_{TH} = 11mV) over a large sample area of a 2-in wafer quadrant. This is thought to come from the FET structure, for which the threshold voltage is principally determined by the difference in the electron affinities of Ge and GaAs. The high VTHuniformity, as well as the positive FET characteristics (g_{m} = 170mS/mm,V_{TH} = 0.25V), makes n+-Ge-HFET very attractive for LSI application.     

High microwave and ultra-low noise performance of fullyion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 μm demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K_f factor of 1.4 estimated by Fukui's noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high     

A criterion for stationary domain formation in GaAs MESFETs

A one-dimensional model that analyzes the formation of stable, stationary domains in GaAs MESFETs is presented. The method utilizes phase portraits to represent the solutions to the ordinary differential equations that characterize the situation in the channel of the device. Two necessary conditions for the formation of stationary domains are revealed. One of these relates to the gate length and can be used to improve upon the commonly used criterion for domain formation of a doping-density minimum-gate-length product of >10¹² cm^-3     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

Gate-voltage dependence of source and drain series resistances andeffective gate length in GaAs MESFETs

Experimental data and calculated results are presented to show that the source and drain series resistances in GaAs MESFETs are gate-voltage dependent. This dependence is caused by the gate-voltage modulation of the ungated portions of the channel. A simple analytical model is proposed that accounts for this dependence by introducing an effective gate-voltage-dependent gate length. For nominal 1-μm gate devices the effective gate length is 0.2-0.3 μm longer than the metallurgical gate length     

Analysis of nitride storage non-volatile memories with HfSiOx blocking dielectric and TiN metal gate for low power embedded applications

Nitride storage non-volatile memories with hafnium silicate (HfSiO_x) blocking dielectric and titanium nitride (TiN) metal gate aimed at low power embedded applications beyond the 45 nm node, have been fabricated and investigated. In addition to presenting the typical figures of merit of flash memories, the scalability of the devices has been assessed. We have also investigated the physical origin of the observed memory features.     

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V _th = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V _th = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.     

A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs

A new two-dimensional (2-D) analytical model for the threshold voltage of a fully depleted short-channel Si-MESFETs fabricated on the silicon-on-insulator (SOI) has been presented in this paper. The 2-D potential distribution functions in the active layer of the device is approximated as a parabolic function and the 2-D Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. The calculations have been carried out for both uniform and nonuniform doping profiles in two dimensions. The minimum bottom potential is used to monitor the drain-induced barrier lowering effect and consequently an analytical expression for the threshold voltage of the device has been derived. The numerical results for the bottom potential and threshold voltage considering a wide range of device parameters have also been presented. The model has been compared with the simulated results obtained by using the ATLAS Device Simulation Software to show the validity of the proposed model. For uniform doping profile, the numerical results have also been compared with the reported data in the literature and a good agreement is observed among the three. The proposed model is simple and easy to understand the behavior of the fully depleted short-channel SOI-MESFETs as compared to the other models reported in the literature.