Impact of parameter fluctuations on RF stability performance of DG Tunnel FET

This paper presents the impact of parameter fluctuation due to process variation on radio frequency (RF) stability performance of double gate tunnel FET (DG TFET). The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit (FoM) such as cut-off frequency (f_t), maximum oscillation frequency (f_max) along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines of DG TFET for RF applications.     

RF performance enhancement in multi-fin TFETs by scaling inter fin separation

This paper deals with the extraction of RF metrics of multi-fin Tunnel FET (TFET) with the inter fin separation (IFS) scaled up to 1 nm. The structure of multi-fin TFET is designed by varying the number of fins (N) from 1 to 5. As the number of fins increases, the drive current (I_D) gets multiplied and the maximum I_D of 76 µA can be achieved for N = 5. Higher I_D is obtained without compromising the leakage current (I_OFF) which is in the range of femto amperes. For the various values of IFS, RF metrics such as intrinsic gain (A₀), unity gain cut-off frequency (f_t), maximum oscillation frequency (f_max), and admittance (Y) parameters are extracted for multi-fin TFETs. The results show for lesser values of IFS, higher intrinsic gain is obtained and the value does not affect as N increases. The maximum value of f_t and f_max is obtained because of the electrostatic coupling between the two adjacent fins. The Y parameters are extracted at an operating frequency of 10 GHz. It can be seen that Y parameters offer better values as the number of fins and IFS increases. This is due to the larger value of gate to drain capacitance (C_gd) which occurs because of the parasitic effect for higher values of IFS.     

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.     

最大振荡频率为200 GHz的蓝宝石衬底AlGaN/GaN HEMT

本文报道了fmax为200GHz的基于蓝宝石衬底的AlGaN/GaN 高电子迁移率晶体管（HEMT）。外延材料结构采用了InGaN背势垒层来减小短沟道效应,器件采用了凹栅槽和T型栅结合的工艺,实现了Ka波段AlGaN/GaN HEMT。器件饱和电流达到1.1A/mm,跨导为421mS/mm,截止频率（fT）为30GHz,最大振荡频率（fmax）为105GHz。采用了湿法腐蚀工艺将器件的Si3N4钝化层去除后,器件的Cgs和Cgd减小,器件截止频率提高到50GHz,最大振荡频率提高到200GHz。     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

A novel SOI-MESFET with symmetrical oxide boxes at both sides of gate and extended drift region into the buried oxide

In this paper a novel structure for silicon on insulator metal semiconductor field effect transistors (SOI MESFETs) is proposed. The proposed structure contains two symmetrical oxide boxes at both sides of gate metal and extended drift region into the buried oxide which is named SO-ED-SOI-MESFET. SO-ED stands for symmetrical oxide boxes and extended drift region. DC and radio frequency characteristics of the SO-ED are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-SOI MESFET) characteristics. The obtained results demonstrate the superiorities of the proposed structure over C-SOI MESFET including increased breakdown voltage, higher driving current and improved RF characteristics. The extended drift region improves the current capability by increasing the effective channel thickness. The oxide region boosts the breakdown voltage due to its high tolerable electric field. Also, RF performance of the device is enhanced because of modified gate-source and gate-drain capacitances in the proposed structure. Unilateral power gain, maximum available gain and current gain experience 63, 52 and 63.5% improvement by applying the proposed structure, respectively. Thus the proposed structure can be considered as a proper candidate for using in high power and high frequency applications.     

基于60 nm T型栅fT & fmax为170 & 210 GHz 的InAlN/GaN HFETs 器件

基于蓝宝石衬底InAlN/GaN异质结材料研制具有高电流增益截止频率(fT)和最大振荡频率(fmax)的InAlN/GaN异质结场效应晶体管 (HFETs)。基于再生长n GaN欧姆接触工艺实现了器件尺寸的缩小,有效源漏间距(Lsd)缩小至600 nm。此外,采用自对准栅工艺制备60 nm T型栅。由于器件尺寸的缩小,在Vgs= 1 V下,器件最大饱和电流(Ids)达到1.89 A/mm,峰值跨导达到462 mS/mm。根据小信号测试结果,外推得到器件的fT和fmax分别为170 GHz和210 GHz,该频率特性为国内InAlN/GaN HFETs器件频率的最高值。     

Microwave power double-heterojunction HEMT's

The RF and dc characteristics of microwave power double-heterojunction HEMt's (DH-HEMT's) with low doping density have been studied. Small-signal RF measurements indicated that the cutoff frequency and the maximum frequency of oscillation in DH-HEMT's with 0.8-1 µm gate length and 1.2 mm gate periphery are typically 11- 16 GHz and 36-41 GHz, respectively. However, the cutoff frequency in DH-HEMT's degrades strongly with increasing drain bias voltage. This may be caused by both effects of increasing effective transit length of electrons and decreasing average electron velocity, due to Gunn domain formation. In large-signal microwave measurement, the DH-HEMT (2.4 mm gate periphery) delivered a maximum output power of 1.05 W with 2.8 dB gain and 0.58 W with 1.6 dB gain at 20 and 30 GHz, respectively. These are the highest output powers yet reported for HEMT devices. For the dc characteristics, the onset of two-terminal gate breakdown voltage is found to correlate with the drain current Idssand recessed length, and three-terminal source-drain breakdown characteristics near pinchoff are limited by the gate-drain breakdown. A simple model on gate breakdown voltage in HEMT is also presented.     

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.      

DC and analog/RF performance optimisation of source pocket dual work function TFET

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n⁺ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.     

埋氧沟槽栅双极模式JFET的仿真与实验

提出了埋氧沟槽栅双极模式JFET(BTB-JFET),其在栅极区域下面添加埋氧以减小栅漏电容Cgd.首次通过仿真对包括BTB-JFET、常规的无埋氧层的沟槽栅双极模式JFET(TB-JFET)和现在正在广泛应用的Trench-MOSFET(T-MOSFET)等20V级的功率开关器件在高频应用时的功率损耗进行了比较,得到有重要意义的结论.采用阻性负载电路.仿真结果表明,与T-MOSFET和常开型TB-JFET相比,常开型BTB-JFET在1MHz时开关功耗分别降低了37%和14%.进行实验以证明仿真上作的合理性,首次成功地制造出常开型BTB-JFET和TB-JFET,其中埋氧结构是通过热氧化的方法实现的.实验结果表明,与TB-JFET相比,在源漏零偏压时,BTB-JFET的Cgd减小了45%;在1MHz时,其开关时时与开关功耗分别降低了约7.4%和11%.因此常开型BTB-JFET应是今后低压高频功率开关器件的研究发展方向.     

InAlAs/InGaAs/InP HEMTs with high breakdown voltages using double-recess gate process

The DC and RF performance of InAlAs/InGaAs/InP HEMTs fabricated using a double-recess gate process are reported. A gate-drain breakdown voltage as high as 16 V was observed. The HEMTs also exhibited a high source-drain breakdown voltage near pinchoff of 16 V and a low RF output conductance of 6 mS/mm. For a 1.4 mu m gate length, an intrinsic transconductance of 560 mS/mm and f/sub T/ and f/sub max/ values of 16 and 40 GHz, respectively, were achieved.<>     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.     

Study of process induced variability of germanium-pTFET in analog and RF domain

Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100 nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. In this brief, we have investigated the two main process induced variability a) the thickness of the germanium body b) the thickness of gate oxide in Ge-pTFET using Sentaurus TCAD device simulation. The analysis is performed in complete analog domain along with the study of intrinsic RF performance parameters using small signal equivalent model with non-quasi static effect of the device under consideration. The process induced variability is estimated on the figure of merits (FOMs) such as drain current (I_ds), transconductance (g_m), output resistance (R_o), intrinsic gain (g_mR_o), unity-gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX), transport delay (τ_m), intrinsic resistance (R_gd) and intrinsic capacitances (C_gs, C_gd).     

Insights into channel potentials and electron quasi-Fermi potentials for DGtunnel FETs

A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed (as in the case of the DG MOSFET); instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential (eQFP) decreases as the channel potential starts to decrease, and there are hiphops in the channel eQFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I-V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.     

Modelling doping design in nanowire tunnel-FETs based on group-IV semiconductors

The tunnel field-effect transistor (TFET), which utilises the band-to-band tunnelling mechanism for current conduction, provides the ability to achieve extremely low subthreshold swing (<60 mV/dec) and very low off-current, thus offering a performance advantage over conventional inversion-mode metal-oxide-semiconductor field effect transistors (MOSFETs) for the ultra-low power and ultra-low voltage operation for the next generation of transistors. In particular, the optimisation of the TFET architecture and material composition is very important because the full potential of the TFET is not yet uncovered. In this work homo- and hetero-structure nanowire TFETs, based on Si, Ge and SiGe materials, have been investigated using device simulation, for the design of source and drain doping profiles, with nanowire diameters down to 5 nm.     

Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode

In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V.     

A model for the electric field in lightly doped drain structures

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor and voltage improvement, indicating the effectiveness of an LDD design in reducing the peak channel field, are used to compare LDD structures with, without, and with partial gate/drain overlap. Approximate equations have been derived that show the dependencies of the field reduction factor on bias conditions and process parameters. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor/voltage improvement and the series resistance are presented for the three cases. Structures with gate-drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate-drain offset can cause the rise of channel field and substrate current at large gate voltages. This offset is also found to be responsible for nonsaturation of drain current. The model has also been compared with two-dimensional simulation results.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.