一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

A 1 GHz CMOS RF front-end IC for a direct-conversion wirelessreceiver

An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 μm CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers     

一种ISM 2.4GHz的低功耗低中频射频接收机前端

本文描述了一种工作在2.4GHz ISM频段的低功耗、低中频射频接收机前端电路,使用TSMC 0.13um CMOS工艺。整个前端包括一个低噪声放大器以及两次变频下变换混频器。低噪声放大器通过在输入级引入额外的栅-源电容实现了低功耗与低噪声的设计;在下变换混频器设计中,分别使用一个单平衡射频混频器以及两个双平衡低中频混频器实现两次变频下变换技术;射频混频器输入晶体管源极串联电感-电容谐振网络以及低噪声放大器输出级的电感-电容谐振网络总共实现了30dB的镜像抑制率。整个前端占用芯片面积约0.42mm2,在1.2V的供电电压下,仅耗功率4.5mW,实现了4dB的噪声系数,在高增益模式下,获得-22dBm的三阶交调线性度,整个链路电压增益为37dB。     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

A low-power multi-band CMOS RF receiver front-end for ubiquitous sensor network applications

This paper presents the design and experimental results of a low-power multi-band RF receiver including a multi-band low-noise amplifier (LNA) and a down-conversion mixer based on the IEEE 802.15.4 standard for sensor node applications. A multi-band LNA with two inputs is tuned to two resonant frequencies by controlling the voltage on a switched MOS. The implemented RF receiver front-end achieves a maximum voltage conversion gain of 38 and 30 dB, NF of 6.2 and 9.2 dB at the 868/915 MHz and the 2.45 GHz bands, respectively. The RF receiver front-end dissipates total 3.0 mA (including I/Q mixers) under supply voltage of 1.8 V at both operation bands.     

A planar wideband 80-200 GHz subharmonic receiver

A wideband planar subharmonic mixer has been designed for millimeter-wave operation. The receiver consists of a back-to-back Schottky-diode pair integrated at the base of a wideband log-periodic antenna and placed on a silicon lens. The wideband planar receiver results in state-of-the art-performance at 90 GHz (and 182 GHz) with a double-sideband conversion loss and noise temperature of 6.7 dB (and 8.5 dB) and 1080 K (and 1820 K), respectively. These results are about 3 dB higher than the results for best tuned waveguide subharmonic mixers using planar diodes. The design is well suited for higher frequencies (up to 1 THz) and for the inclusion of biased back-to-back planar diodes to ease the LO power requirements. The planar subharmonic approach results in an inexpensive wideband receiver, and the design can be easily extended to receiver arrays     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

A 60-GHz CMOS receiver front-end

The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-/spl mu/m CMOS technology, the receiver front-end provides a voltage gain of 28 dB with a noise figure of 12.5 dB while consuming 9 mW from a 1.2-V supply.     

一种应用于6-9GHz UWB系统的低噪声CMOS射频前端设计

本文介绍了一种应用于6-9 GHz超宽带系统的全集成差分CMOS射频前端电路设计。在该前端电路中应用了一种电阻负反馈形式的低噪声放大器和IQ两路合并结构的增益可变的折叠式正交混频器。芯片通过TSMC 0.13µm RF CMOS工艺流片,含ESD保护电路。经测试得该前端电路大电压增益为23~26dB,小电压增益为16~19dB;大增益下前端电路平均噪声系数为3.3-4.6dB,小增益下的带内输入三阶交调量(IIP3)为-12.6dBm。在1.2V电压下,消耗的总电流约为17mA。     

A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering

A CMOS wideband front-end IC is demonstrated in this paper.It consists of a low noise transconductance amplifier（LNTA） and a direct RF sampling mixer（DSM） with embedded programmable discrete-time filtering.The LNTA has the features of 0.5-6 GHz wideband,wideband input matching and low noise.The embedded filter following the DSM operates in discrete-time charge domain,filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency.The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz.It shows a conversion gain of 12.6 dB and IP_1dB of-7.5 dBm at 2.4 GHz.It occupies a chip area of 0.23 mm² and consumes 14 mA DC current.     

采用内嵌了离散时间滤波器的射频直接采样混频器的CMOS宽带前端芯片

本文展示了一种新型的CMOS宽带射频前端芯片。它由低噪声跨到放大器（LNTA）和内嵌了可编程的离散时间滤波器的射频直接采样混频器（DSM）组成。第一级的LNTA具有0.5到6GHz的带宽,宽带输入匹配以及低噪声的特性。DSM之后的内嵌滤波器工作在离散时间电荷域,可以根据始终频率控制中频带宽,同时滤除混叠和干扰信号。测试结果显示,在0.5到6GHz的带宽内,噪声系数均低于7dB。在2.4GHz处,转换增益为12.6dB,IP1dB为-7.5dBm。该芯片所占面积为0.23mm2,消耗14mA直流电流。     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.