采用内嵌了离散时间滤波器的射频直接采样混频器的CMOS宽带前端芯片

本文展示了一种新型的CMOS宽带射频前端芯片。它由低噪声跨到放大器（LNTA）和内嵌了可编程的离散时间滤波器的射频直接采样混频器（DSM）组成。第一级的LNTA具有0.5到6GHz的带宽,宽带输入匹配以及低噪声的特性。DSM之后的内嵌滤波器工作在离散时间电荷域,可以根据始终频率控制中频带宽,同时滤除混叠和干扰信号。测试结果显示,在0.5到6GHz的带宽内,噪声系数均低于7dB。在2.4GHz处,转换增益为12.6dB,IP1dB为-7.5dBm。该芯片所占面积为0.23mm2,消耗14mA直流电流。     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².     

A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering

A CMOS wideband front-end IC is demonstrated in this paper.It consists of a low noise transconductance amplifier（LNTA） and a direct RF sampling mixer（DSM） with embedded programmable discrete-time filtering.The LNTA has the features of 0.5-6 GHz wideband,wideband input matching and low noise.The embedded filter following the DSM operates in discrete-time charge domain,filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency.The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz.It shows a conversion gain of 12.6 dB and IP_1dB of-7.5 dBm at 2.4 GHz.It occupies a chip area of 0.23 mm² and consumes 14 mA DC current.     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

一款集成驱动放大器的低变频损耗混频器设计

采用0.5μm GaAs工艺设计并制造了一款单片集成驱动放大器的低变频损耗混频器.电路主要包括混频部分、巴伦和驱动放大器3个模块.混频器的射频(RF)、本振(LO)频率为4～7 GHz,中频(IF)带宽为DC～2.5 GHz,芯片变频损耗小于7 dB,本振到射频隔离度大于35 dB,本振到中频隔离度大于27 dB.1 dB压缩点输入功率大于11 dBm,输入三阶交调点大于20 dBm.该混频器单片集成一款驱动放大器,解决了无源混频器要求大本振功率的问题,变频功能由串联二极管环实现,巴伦采用螺旋式结构,在实现超低变频损耗和良好隔离度的同时,保持了较小的芯片面积.整体芯片面积为1.1 mm×1.2 mm.     

宽中频CMOS下变频器单片

该文介绍了一种工作于毫米波频段的宽中频(IF)下变频器.该下变频器基于无源双平衡的设计架构,片上集成了射频(RF)和本振(LO)巴伦.为了优化无源下变频器的增益、带宽和隔离度性能,电路设计中引入了栅极感性化技术.测试结果表明,该下变频器的中频带宽覆盖0.5～12?GHz.在频率为30?GHz、幅度为4?dBm的LO信号...     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a ? 10.8 dBm IIP3 with a power consumption of 0.9 mW.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

InAlAs/InGaAs HBT X-band double-balanced upconverter

We report on an InAlAs/InGaAs HBT Gilbert cell double-balanced mixer which upconverts a 3 GHz IF signal to an RF frequency of 5-12 GHz. The mixer cell achieves a conversion loss of between 0.8 dB and 2.6 dB from 5 to 12 GHz. The LO-RF and IF-RF isolations are better than 30 dB at an LO drive of +5 dBm across the RF band. A pre-distortion circuit is used to increase the linear input power range of the LO port to above +5 dBm. Discrete amplifiers designed for the IF and RF frequency ports make up the complete upconverter architecture which achieves a conversion gain of 40 dB for an RF output bandwidth of 10 GHz. The upconverter chip set fabricated with InAlAs/InGaAs HBT's demonstrates the widest gain-bandwidth performance of a Gilbert cell based upconverter compared to previous GaAs and InP HBT or Si-bipolar IC's     

太赫兹宽带分谐波混频器设计

太赫兹分谐波混频器的变频损耗、噪声系数等指标与基波混频器相近,且本振频率为射频频率的一半,大大 降低了本振源的设计难度和制作成本,是高性能太赫兹接收前端的关键部件。本文介绍了一种覆盖全波导带宽的太赫 兹宽带分谐波混频器的设计,对电路中射频波导至悬置带线过渡结构和本振中频双工器进行仿真和优化设计。并以 0.14~0.22THz 分谐波混频器为例进行设计和制作,测试结果表明0.14 ~0.22THz 分谐波混频器在全波导频段内最大变频 损耗低于15dB,中频3dB 带宽大于20GHz。     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

Broadband single- and double-balanced resistive HEMT monolithicmixers

A double-balanced (DB) 3-18 GHz and a single-balanced (SB) 2-16 GHz resistive HEMT monolithic mixer have been successfully developed. The DB mixer consists of a AlGaAs/InGaAs HEMT quad, an active LO balun, and two passive baluns for RF and IF. At 16 dBm LO power, this mixer achieves the conversion losses of 7.5-9 dB for 4-13 GHz RF and 7.5-11 dB for 3-18 GHz RF. The SB mixer consists of a pair of AlGaAs/InGaAs HEMT's, an active LO balun, a passive IF balun and a passive RF power divider. At 16 dBm LO power, this mixer achieves the conversion losses of 8-10 dB for 4-15 GHz RF and 8-11 dB for 2-16 GHz RF. The simulated conversion losses of both mixers are very much in agreement with the measured results. Also, the DB mixer achieves a third-order input intercept (IP₃) of +19.5 to +27.5 dBm for a 7-18 GHz RF and 1 GHz IF at a LO drive of 16 dBm while the SB mixer achieves an input IP ₃ of +20 to +28.5 dBm for 2 to 16 GHz RF and 1 GHz IF at a 16 dBm LO power. The bandwidth of the RF and LO frequencies are approximately 6:1 for the DB mixer and 8:1 for the SB mixer. The DB mixer of this work is believed to be the first reported DB resistive HEMT MMIC mixer covering such a broad bandwidth     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

GaAs双栅MESFET单片行波混频器

本文根据GaAs MESFET单片行波放大器的原理,研制了一种新型宽带单片混频器.混频电路制在厚为0.1mm,面积为2.7×1.8mm的GaAs基片上,RF和LO分别通过等效特性阻抗为50Ω的G_1线和G_2线进入混频电路,且这两个频率在4个GaAs双栅MESFET(DGFET)中混频.这种MMIC混频器在中频频率为1.0GHz.射频频率在2～12GHz范围内得到约为8.5dB的变频损耗(无中频匹配电路),其平坦度约为±0.6dB.这一结果有助于进一步研究与实现单片宽带微波接收机.     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

This paper presents a wireless receiver front-end intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs positive feedback with transistors biased in the sub-threshold region, resulting in cancellation of the third order non-linearity. The mixers are also linearized, using a baseband to LO bootstrap circuit. Measurements of the front-end show about 3.5 dB improvement in out-of-band IIP3 at optimum bias of the positive feedback devices in the LNA, resulting in an out-of-band IIP3 of 10 dBm. With a frequency range from 0.7 to 3 GHz the receiver front-end covers most important cellular bands, with an input return loss above 9 dB and a voltage gain exceeding 16 dB for all bias settings. The circuit consumes 4.38 mA from a 1.5 V supply.