Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO₂, while the subthreshold slope for fixed values of V_g remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an I_on/I_off ratio of more than 2 times 10¹¹ is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.     

Nanoscale Ⅲ-Ⅴ on Si-based junctionless tunnel transistor for EHF band applications

A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor (SG-JLTFET) has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as ION,ION/IOFF,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET (DG-JLTFET).The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.     

Temperature Effects on Hetero Structure Junctionless Tunnel FET

For the first time, we investigate the temperature effect on Al Ga As/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope(< 60 m V/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

Cryogenically Cooled GaAs FET Amplifier with a Noise Temperature Under 70 K at 5.0 GHz (Short Papers)

A 4.5-5.0-GHz gallium arsenide field-effect transistor (GaAs FET) amplifier cryogenically cooled to approximately 70 K is described. A noise temperature of under 70 K is achieved over the hand. Power gain for the two-stage amplifier is 20 dB. A noise analysis is performed to predict noise-temperature dependence on the temperature of the amplifier.     

Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate

Numerical simulation-based study of double-gate (DG) field-effect transistors (FETs) leads to the possibly viable concept of extremely scaled but nonself-aligned DG CMOS. Predictions of off-state current, on-state current, and circuit performance, accounting for short-channel effects and energy-quantization effects, in 25-nm DG FETs suggest that moderate back-gate underlap does not severely undermine the superior performance and leakage current of nanoscale DG CMOS relative to those of bulk-Si CMOS. The reverse back-gate biasing scheme for leakage reduction in DG CMOS is shown to be much more efficient than the reverse body biasing scheme in bulk Si even with moderate back-gate underlap.     

Low-Noise Receiver Design Trends Using State-of-the-Art Building Blocks

The current state-of-the-art and the various design tradeoffs encompassing the variety of low-noise microwave and millimeter-wave receiver "building blocks" which have evolved during the past two decades are described. Key examples of these are the high-idler non-cryogenic parametric amplifier, the gallium arsenide field-effect transistor (GaAs FET) amplifier, and the image-enhanced Schottky-diode mixer. It is then shown how this inventory of building blocks can best be integrated into optimum receiver configurations for application in a multiplicity of future and present microwave and miltimeter-wave communications, RADAR, and radiometer systems.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

GaAs enhancement mode FET-tunnel diode ultra-fast low power inverter and memory cell

A microtunnel diode load for a normally off enhancement mode gallium arsenide field effect transistor provides a compact inverter circuit of fast switching speed and low power consumption. Level shifting is not required, and direct coupling with multiple fan-out causes a comparatively small decrease in speed. The tunnel diode FET logic (TDFL) should be capable of operation at 2 GHz with a power-delay time product of 3.4 fJ for an output node capacitance of 50 fF. The negative characteristic of the tunnel diode combined with the FET provides a compact memory cell. However, advances in the state of the art for producing microtunnel diodes of precisely controlled peak current will be required before a viable TDFL can emerge.     

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s.     

Femtojoule high speed planar GaAs E-JFET logic

An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.     

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson–SchrÖdinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.     

MBE growth and electrical behaviour of single and double Si δ-doped InGaAs-layers

The use of δ-doping to form the channel of a field-effect transistor (FET) was proposed earlier to give better pinch-off behaviour, higher transconductance, and high drain-gate breakdown voltages compared to a uniformly doped channel layer. In the present work δ-doping of InGaAs MBE grown layers using Si is investigated. Furthermore, the design of an improved δ-doped JFET is proposed which comprises double δ-doped atomic planes within the channel layer to increase the effective carrier mobility and saturated drift velocity. Consequently higher transconductance and frequency limits are expected. Reduced sheet resistance values have been measured in double δ-doped channels compared to single δ-doped channels comprising the same sheet concentration.     

Short-channel GaAs FET fabricated like a MESFET but operating like a JFET

Normally-on GaAs field-effect transistors (FETs) having 1 ?m gate lengths and 4 ?m channel lengths were fabricated in structures grown by molecular beam epitaxy (MBE). The unique part of this device is the very thin p+/n+ structure used to replace the conventional Schottky barriers. The device fabrication procedure is identical to that of a Schottky barrier FET (MESFET), but the devices exhibit characteristics similar to that of a junction field-effect transistor (JFET). This new device, the `camel diode gate FET?, is expected to have applications in both logic and power devices.     

Recent Advances in Gallium Phosphide Junction Devices for High-Temperature Electronic Applications

Recent advances in gallium phosphide technology are reviewed as they relate to high-temperature (T > 300°C) device applications. The electronic properties and materials aspects of GaP are summarized and compared to silicon and gallium arsenide. Minority-carrier unction devices are discussed as one area where this technology could have wide application. In this light, the high-temperature operation of two junction devices, a diode and a bipolar junction transistor (BJT), are displayed. The GaP diode is observed to provide excellent rectification properties with very low leakage over the full temperature range from 20°C to 400°C (< 3x10 -3A/cm2 at VR = 3 V, T = 400°C) and has demonstrated stable operation under bias for over 1000 h at 300°. The bipolar transistor has demonstrated constant current gain (6 < ? B < 10) and very low collector-base leakage for temperatures up to 450°C (ICO 80 μA at VCB = 3 V, T = 450°C). The contacting technology to GaP is identified as one area where additional work is necessary.     

Tunnel field-effect transistors with graphene channels

The lack of an OFF-state has been the main obstacle to the application of graphene-based transistors in digital circuits. Recently vertical graphene tunnel field-effect transistors with a low OFF-state current have been reported; however, they exhibited a relatively weak effect of gate voltage on channel conductivity. We propose a novel lateral tunnel graphene transistor with the channel conductivity effectively controlled by the gate voltage and the subthreshold slope approaching the thermionic limit. The proposed transistor has a semiconductor (dielectric) tunnel gap in the channel operated by gate and exhibits both high ON-state current inherent to graphene channels and low OFF-state current inherent to semiconductor channels.     

SiO/sub 2//AlGaN/InGaN/GaN MOSDHFETs

The characteristics of a novel nitride based field-effect transistor combining SiO/sub 2/ gate isolation and an AlGaN/InGaN/GaN double heterostructure design (MOSDHFET) are reported. The double heterostructure design with InGaN channel layer significantly improves confinement of the two-dimensional (2-D) electron gas and compensates strain modulation in AlGaN barrier resulting from the gate voltage modulations. These decrease the total trapped charge and hence the current collapse. The combination of the SiO/sub 2/ gate isolation and improved carrier confinement/strain management results in current collapse free MOSDHFET devices with gate leakage currents about four orders of magnitude lower than those of conventional Schottky gate HFETs.     

The Complete Semiconductor Transistor and Its Incomplete Forms

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor,BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.     

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies

Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.      

Electrical transport properties in electroless-etched Si nanowire field-effect transistors

We report the electrical transport of the Si nanowires in a field-effect transistor (FET) configuration, which were synthesized from B-doped p-type Si(1 1 1) wafer by an aqueous electroless etching method based on the galvanic displacement of Si by the reduction of Ag⁺ ions on the wafer surface. The FET performance of the as-synthesized Si nanowires was investigated and compared with Ag-nanoparticles-removed Si nanowires. In addition, high-k HfO₂ gate dielectric was applied to the Si nanowires FETs, leading to the enhanced performance such as higher drain current and lower subthreshold swing.