一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.     

0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。     

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout(LDO)regulator for system-on-chip(SoC)applications is presented.By adopting AC-boosting and active-feedback frequency compensation(ACB-AFFC),the proposed LDO enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high.The LDO regulator is designed and fabricated in a 0.6/am CMOS process.The active silicon area is only 770×472μm2.Experimental results show that the total error of the output voltage due to line variation is less than ±0.1 97%.The load regulation is only 0.35 mV/mA when the load current changes fromoto 100mA.     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对(极零对的产生没有增加静态功耗),不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作.由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要;而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度.该LDO基于0.5μm CMOS工艺实现.后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压(dropout电压)仅为120mV.     

一种用于LDO稳压器的共享预稳压电路

提出了一种用于LDO稳压器的共享预稳压电路.该共享预稳压电路中包含一个电源抑制减法电路以提高基准源的电源抑制,应用电流负反馈结构以降低基准源的温度系数和电源抑制随工艺阈值电压变化的敏感度,还可以降低LDO稳压器的输出噪声.仿真结果表明在阈值电压发生士20％变化的情况下,基准源的温度系数变化只有0.11×10-6/℃,电...     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

Current buffer compensation topologies for LDOs with improved transient performance

The goal of internal frequency compensation of a low dropout voltage regulator (LDO) is the selection of a small-value, ESR-independent output capacitor. Cascode compensation formed by a common-gate transistor acting as a current buffer, an optional series resistor, and a compensation capacitor creates a dominant pole and a left-half-plane (LHP) zero, allowing adequate phase margin and stable LDO design. To this end, a 1.21?V output, 100?mA, 0.1?C10???F output capacitor, ESR-independent, low voltage LDO using cascode compensation with replica bias is designed and fabricated in a 0.5???m CMOS process with an area of 0.22?mm². A line regulation of 0.05% V/V, load regulation of 0.001% V/mA and dropout voltage of 220?mV were measured. LDO-specific pole-zero analysis is detailed. In addition to this design, two improved transient response LDO architectures using cascode compensation with split-length transistors are also explored. A Power Good feature is discussed, which enables direct interface between the LDO and a micro-processor.     

一款采用超前相位补偿技术的低压差线性稳压器

设计了一种具有高稳定性、能够驱动较大负载电流的低压差线性稳压器(LDO)电路,输入电压为3.0~6.0 V,输出电压为2.8 V。采用超前相位补偿技术,产生一组零极点对,零点补偿前面环路中的极点,使得LDO电路具有稳定的环路结构,得到稳定的输出电压。基于CSMC 0.25μm EN BCDMOS工艺完成电路和版图的设计。电路仿真结果表明电路的负载调整率为0.03%/A,线性调整率为0.13%/V,最大驱动的负载电流为10 mA。在不同负载条件下,LDO环路的最差相位裕度能够达到64.1°。     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

一种全集成型CMOS LDO线性稳压器设计

设计了一种基于0.25μm CMOS工艺的低功耗片内全集成型LDO线性稳压电路。电路采用由电阻电容反馈网络在LDO输出端引入零点,补偿误差放大器输出极点的方法,避免了为补偿LDO输出极点,而需要大电容或复杂补偿电路的要求。该方法电路结构简单,芯片占用面积小,无需片外电容。Spectre仿真结果表明：工作电压为2.5 V,电路在较宽的频率范围内,电源抑制比约为78 dB,负载电流由1 mA到满载100 mA变化时,相位裕度大于40°,LDO和带隙电压源的总静态电流为390μA。     

采用增强型AB跟随器的快速响应LDO

设计了一种采用增强型AB跟随器作为缓冲器的快速响应LDO.利用跟随器的动态电流提高能力,显著地改善了误差放大器对功率MOS管寄生大电容的驱动;同时,由负反馈引起的阻抗降低效应将功率管的寄生电容极点推到了更高的频率,提高了环路的相位裕度.采用TSMC0.35-μm CMOS工艺进行仿真,当负载电流在0.1μs内从1 mA跳变到50 mA以及从50 mA跳变到1 mA时,相对于同等条件下的源跟随器LDO,输出峰值分别减少4 mV和46 mV,且稳定时间只需要0.2 μs和0.5 μs.     

一种采用新颖的双重自适应补偿的低静态电流LDO稳压器的设计

设计了一种采用双重自适应补偿的两级结构LDO线性稳压器,该补偿技术能够产生两个随负载变化的零点以抵消不同负载条件下的极点变化带来的影响,从而保证系统的稳定性.与传统的设计方法相比,该补偿方法几乎不消耗电流,文中设计的LDO静态电流小于1μA,并且采用折返式电流限制,减小了芯片的功耗.采用该双重自适应补偿的LDO已在Hynix O.5μm CMOS工艺线投片,当负载电流为300mA时,漏失电压为150mV,线性调整率为2mV/V,负载调整率为0.75%.测试结果表明,采用该双重自适应补偿结构的LDO工作良好.     

用于射频SOC芯片的低噪声高电源抑制比LDO

设计了一种能够为射频芯片提供低噪声、高PSRR、全集成LDO.采用SMIC 0.18μmRF工艺实现,芯片有效面积0.11 mm2.测试结果表明:当输出电流从0跳变为20 mA时,最大Ripple 为100 mV,稳定时间2μs;当输出电流为20mA,频率到1 MHz的情况下,PSRR＜-30 dB;从1～100 kH...     

一种1.2V,80mA,5μF快速瞬态响应、高稳定性LDO的设计

基于上华0.5μm工艺,设计了输入电压为1.5V,输出电压为1.2V,最大输出电流为80mA,用于DC/DC里的CMOS低压差线性稳压器(Low-dropout regulator),作为带隙基准输出端的后续模块,以达到滤波和提高参考电压精度的目的。提出了一种补偿网络,可以保证负载电流发生变化时,相位裕量不发生变化;在补偿网络的基础上添加一个感应电容能够快速跟踪极点的变化,从而保证在负载电流跳变瞬间稳定性保持不变,防止了输出电压发生振荡的情形。此外,设计了一种瞬态响应提高电路结构来改善负载瞬态响应。仿真结果表明,在tt corner下该LDO线性稳压器在负载电流为1mA和80mA时的相位裕度均为83°,环路增益为80dB,流片测试结果显示过冲电压和欠冲电压均不超过100mV。     

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out(LDO) regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV(0.7%) overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.     

一种超低静态电流LDO线性稳压器的设计

为了延长便携式、可穿戴医疗设备的待机时间,设计了一种具有超低静态电流的低压差(LDO)线性稳压器。采用误差放大器与基准电路相结合的结构,在降低静态电流的同时减小芯片面积;其次,利用负载检测模块,降低了空载及轻载时过温保护和过流保护等模块的静态电流。采用自适应偏置电流技术来动态调整稳压环路各支路的工作电流以及零点频率补偿方式,解决了静态功耗与瞬态响应和环路带宽间的矛盾。该LDO线性稳压器采用0.35μm CMOS工艺进行流片加工,测试结果表明,该LDO线性稳压器静态电流为700 nA,最大负载电流为150 mA,轻载与满载跳变时上过冲电压为63 mV,下过冲电压为55 mV。     

FVF‐Based Low‐Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

A new internally compensated low drop‐out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65‐nm CMOS technology. Measurements show load and line regulations of 433.80 μV/mA and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of 1 μs. The total current consumption is 17.88 μA (for a 0.9 V supply voltage).     

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90?nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3???V/mA with a 1.2?V input and 1?V output. For a 100?mA load current step with the rise/fall time of 100?ps, the LDO achieves maximum output voltage drop and overshoot of less than 95?mV when loaded by a 600?pF decoupling capacitor and consumes an average bias current of 408???A. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005?mm². Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.     

一种低静态电流、高稳定性的LDO线性稳压器

该文提出了一种低静态电流、高稳定性低压差(LDO)线性稳压器。LDO中的电流偏置电路产生30nA的低温度漂移偏置电流,可使LDO的静态工作电流降低到4A。另外,通过设计一种新型的动态Miller频率补偿结构使得电路的稳定性与输出电流无关,达到了高稳定性的设计要求。芯片设计基于CSMC公司的0.5m CMOS混合信号模型,并通过了流片验证。测试结果表明,该稳压器的线性调整和负载调整的典型值分别为2mV和14mV;输出的最大电流为300mA;其输出压差在150mA输出电流,3.3V输出电压下为170mV;输出噪声在频率从22Hz到80kHz间为150VRMS。