Suppression of parasitic bipolar effects in thin-film SOItransistors

In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n^- drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5-μm gate length, a maximum holding voltage in excess of 6 V has been simulated     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

12-kV p-Channel IGBTs With Low On-Resistance in 4H-SiC

SiC bipolar devices are favored over SiC unipolar devices for applications requiring breakdown voltage in excess of 10 kV. We have designed and fabricated p-channel insulated-gate bipolar transistors (IGBTs) in 4H-SiC with 12-kV blocking voltage for high-power applications. A differential on-resistance of 18.6 $hbox{m}Omegacdothbox{cm}^{2}$ was achieved with a gate bias of 16 V, corresponding to a forward voltage drop of 5.3 V at 100 $ hbox{A/cm}^{2}$, indicating strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintaining a high carrier lifetime for conductivity modulation. The p-channel IGBT (p-IGBT) exhibits a transconductance that is $hbox{3}times$ higher than that of the 12-kV n-channel SiC IGBTs. An inductive switching test was done at 1.5 kV and 0.55 A $(sim !!hbox{140} hbox{A/cm}^{2})$ for the p-IGBTs, and a turn-on time of 40 ns and a turn-off time of $sim !!hbox{2.8} muhbox{s}$ were measured.      

Photo-CVD SiO/sub 2/ layers on AlGaN and AlGaN-GaN MOSHFET

High-quality SiO/sub 2/ was successfully deposited onto AlGaN by photochemical vapor deposition (photo-CVD) using a D/sub 2/ lamp as the excitation source. The resulting interface state density was only 1.1 /spl times/ 10/sup 11/ cm/sup -2/eV/sup -1/, and the oxide leakage current was dominated by Poole-Frenkel emission. Compared with AlGaN-GaN metal-semiconductor HFET (MESHFETs) with similar structure, the gate leakage current is reduced by more than four orders of magnitude by using the photo-CVD oxide layer as gate oxide in AlGaN-GaN metal-oxide-semiconductor heterojunction field-effect transistors (MOSHFETs). With a 2-/spl mu/m gate, the saturated I/sub ds/, maximum g/sub m/ and gate voltage swing (GVS) of the fabricated nitride-based MOSHFET were 572 mA/mm, 68 mS/mm, and 8 V, respectively.     

High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

As the characteristics of insulated gate transistors [like metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of di/dt at turn-on and dv/dt at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.     

槽栅MOS控制的晶闸管

报道了一种新结构的功率栅控晶闸管,称其为槽栅MOS控制的晶闸管（TMCT）.在该器件结构中,采用UMOS控制晶闸管的开启和关闭.结构中不存在任何的寄生器件,因此,消除了在其它结构的栅控晶闸管中由寄生晶体管引起的各种问题,所以TMCT会有优良的电特性.实验结果表明,多元胞TMCT（600V,有源区面积0.2mm2）的开态压降在300A/cm2时为1.25V,最大可控电流在栅压为-20V和电感负载下达到了296A/cm2.     

Integrated injection logic: a new approach to LSI

Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 /spl mu/m. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

Low voltage organic thin film transistors(OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate(PMMA-GMA) as the gate dielectric.The OTFTs performed acceptably at supply voltages of about 10 V.From a densely packed copolymer brush,a leakage current as low as 2×10~(-8) A/cm~2 was obtained.From the measured capacitance-insulator frequency characteristics,a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric,the threshold voltage ...     

2-µm Gate-length enhancement mode InGaAs/InP:Fe-JFET's with high transconductance

Investigations of enhancement mode InGaAs junction field-effect transistors (JFET's) grown on InP:Fe-substrate by liquid-phase epitaxy (LPE) are reported. The JFET's with 2-µm gate length and 190- µm gate width show a threshold voltage of 0.4 V, a low drain current of < 10 µA at 0-V gate-source voltage and a maximum transconductance of 105 mS/mm. The measured transconductances of enhancement mode InGaAs/InP:Fe JFET's with different gate lengths but with the same gate width and threshold voltage decrease proportional to the inverse gate length as expected from a constant drift mobility FET model.     

Ultra-low-power and high-speed SiGe base bipolar transistors forwireless telecommunication systems

Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The SiGe base and a poly-Si/SiGe base-contact were formed by selective growth in a self-aligned manner. The transistors have a very small base-collector capacitance (below 1 fF for an emitter area of 0.2×0.7 μm) and exhibit a high maximum oscillation frequency (30-70 GHz) at low current (5-100 μA). The power-delay product of an ECL ring oscillator is only 5.1 fJ/gate for a 250-mV voltage swing. The maximum toggle frequency of a one-eighth static divider is 4.7 GHz at a switching current of 68 μA/FF     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Improvement of threshold voltage deviation in damascene metal gatetransistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (ΔV _th) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, ΔV_th of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (ΔV_th) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta₂O₅ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN     

Threshold shift calculations for ion implanted MOS devices

The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO₂ interface. These shallow implants (< 0.1 μm) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO₂ is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.     

A high-speed 64K CMOS RAM with bipolar sense amplifiers

A TTL-compatible 64K static RAM with CMOS-bipolar circuitry has been developed using a 1.2-/spl mu/m MoSi gate n-well CMOS-bipolar technology. Address access time is typically 28 ns, with 225 mW active power and 100 nW standby power. A CMOS six-transistor memory cell is used. The cell size is 18/spl times/20 /spl mu/m, and the chip size is 5.95/spl times/6.84 mm. The n-p-n transistors are used in the sense amplifiers, voltage regulators, and level clamping circuits. The bipolar sense amplifiers reduce the detectable bit line swing, thus improving the worst-case bit line delay time and the sensing delay time. In order to reduce the word line delay, the MoSi layer, which has 5 /spl Omega//sheet resistivity, was used for the gate material. The n-well CMOS process is based on a scaled CMOS process, and collector-isolated n-p-n transistors and CMOS are integrated simultaneously without adding any extra process steps and without causing any degradation of CMOS characteristics. The n-p-n transistor has a 2-GHz cutoff frequency at 1 mA collector current.     

Unusually abrupt switching in submicrometer thin-film transistorsusing a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 μm or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations     

The two-dimensional model for the base surface current in integrated bipolar transistors and its applications

The recombination of minority carriers at the Si-SiO₂ interface has a great effect on bipolar devices. In this paper, the surface electrical properties of capacitors (MOS or MNOS) and gate-controlled npn transistors which are passivated by SiO₂ and Si0₂---Si₃N₄ films, respectively, are studied, and it is found that the Si0₂---Si₃N₄ dual dielectrical films can reduce the surface current in the base region. An improved theoretical model of the base surface current versus surface potential or gate voltage is set up on the basis of the work of Hillen and Holsbrink [Solid St. Electron. 26, 453–463 (1983)] for integrated bipolar transistors. The model successfully explains the experimental results of the variation of the base surface current of the gate-controlled integrated bipolar npn transistors with the gate voltage and provides a more accurate model for the computer simulation and the reliability analysis of the devices.