Multibit resonant tunneling diode SRAM cell based on slew-rateaddressing

We propose and demonstrate a resonant-tunneling diode (RTD) based memory cell in which N bits are stored in a series combination of N RTDs without internal node contacts. The slew rate of an applied voltage signal determines the circuit switching dynamics and allows addressing of the bits. We verify slew rate dependent switching order of up to four series RTDs experimentally and through SPICE simulation incorporating a physics-based RTD model. The new addressing scheme allows N bits to be stored in a stack of N vertically integrated RTDs compared to log₂ (N) bits in previous demonstrations. We demonstrate a two-bit two-RTD static memory cell based on the new method     

A ferroelectric-piezoelectric random access memory

A two-dimensional ferroelectric memory array is combined with a piezoelectric interrogation technique to provide a memory device with nonvolatile storage, random access, non-destructive readout and compatibility with integrated circuits. Binary information is stored as either a positive or negative polarization state in ferroelectric ceramic material and is read out by sensing the polarity of the piezoelectric response of the material. Calculations and experimental results are presented for a 5 word × 5 bits per word prototype device for which a complete logic and driving circuit has been designed and used. Switching characteristics, disturb pulse sensitivity, and changes with temperature are presented. Calculations show that word-to-word capacitive coupling will affect the maximum size of the memory and will probably limit the number of words per chip to approximately 25. No such limit exists on the number of bits per word.     

Efficient implementation of error correction codes in hash tables

Hash tables are one of the most commonly used data structures in computing applications. They are used for example to organize a data set such that searches can be performed efficiently. The data stored in a hash table is commonly stored in memory and can suffer errors. To ensure that data stored in a memory is not corrupted when it suffers errors, Error Correction Codes (ECCs) are commonly used. In this research note a scheme to efficiently implement ECCs for the entries stored in hash tables is presented. The main idea is to use an ECC as the hash function that is used to construct the table. This eliminates the need to store the parity bits for the entries in the memory as they are implicit in the hash table construction thus reducing the implementation cost.     

On the power of quantum memory

We address the question whether quantum memory is more powerful than classical memory. In particular, we consider a setting where information about a random n-bit string X is stored in s classical or quantum bits, for s相似文献   

The Trap Technique

A full-scale quantum computer would work like the standard desktop computer, in that it would have a place to store data, a place where a program manipulates the data, and interconnections to move the data from one to the other. In the computer you are using now, bits of data - stored as quantity of charge or its absence - are transferred from memory to a processor in the form of levels of voltage. At the processor the computer's program determines which logic operations the bits will be subjected to. Once the logic operations are completed, the bits are converted to amounts of charge and stored in memory again. Similarly, in an ion-trap computer, stored qubits would be called from a storage trap to a logic trap, the kind we've been building so far. The two traps would be connected by a long trap that acts like an interconnect or a data bus. It sounds simple, but such a structure would have to be repeated and connected many dozens of times on the same chip to handle the number of ions we'd need. Therefore, a quantum computer equivalent of very-large-scale integration would be required to handle the control circuitry just to move the ions around. The small-scale quantum algorithms that scientists are running today and plan to run in the near future will almost certainly lead to insights that could make full-scale quantum computing, if not easy, at least more tractable.     

Large-Capacity Magnetic-Drum Memory System for an Electronic Switching System

A stored program-controlled electronic switching system (ESS) requires a large-capacity memory to store various kinds of programs and data. This paper describes a hierarchy arrangement including a high-speed memory and a low-cost largecapacity magnetic-drum memory for reduction of the cost of the ESS. The paper also describes the design philosophy, reliability, structure, and evaluation of the system. A magnetic drum with hydrodynamic floating heads (memory capacity:3.7 times 10^{7}bits, clock rate: 2.2 MHz) was employed. The magnetic-drum memory system can provide transfer of individual words (each consisting of 41 bits), transfer of variable-length data by flag bit control, and content-addressable access. Furthermore, the system is designed to be most suitable for transfer of the large amount of data required by the switching system. The data throughput of the magnetic-drum memory system is 210 kbytes/s in a burst mode. The mean time between failures (MTBF) of the system is approximately3.5 times 10^{3}h. This system assures reliability required for the ESS and high performance for application of the ESS to stored data switching as well as telephone switching.     

基于微程序技术的存储控制器的研究和设计

以一个应用于网络与通讯领域的SOC芯片研发项目为背景,设计了SOC芯片上的存储控制器.该存储控制器基于动态微程序控制技术,用RAM阵列来存储控制字,在SOC芯片初始化时由用户写入控制字,在芯片工作时,也可通过系统总线对RAM阵列进行写操作,使控制字能动态地改变.该结构的存储控制器具有高度的灵活性,可灵活地根据SOC芯片外接的存储器类型进行配置,能够与多种类型的存储器实现无缝连接使用.相比仅适用于某类型存储器的控制器,该存储控制器具有较大的应用优势.     

A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories

In the conventional content-addressable memory (CAM), equal power is consumed to determine if a stored word is matched to a search word or mismatched, independent of the number of mismatched bits. This paper presents a match-line (ML) sensing scheme that allocates less power to match decisions involving a larger number of mismatched bits. Since the majority of CAM words are mismatched, this scheme results in a significant CAM power reduction. The proposed ML sensing scheme is implemented in a 256 /spl times/ 144-bit ternary CAM for a 0.13-/spl mu/m 1.2-V CMOS logic process. For a 2-ns search time on a 144-bit word, the proposed scheme saves 60% of the power consumed by the conventional sensing scheme.     

A fully decoded 2048-bit electrically programmable FAMOS read-only memory

A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the static mode and 500 ns in the dynamic mode of operation. The memory chip is assembled in a 24-lead dual-in-line package.     

A Software Technique for Diagnosing and Correcting Memory Errors

A software diagnostic that eliminates 2-bit and some 3-bit errors is described. The diagnostic procedure tests memory for errors that cannot be corrected by ECC (error correcting code): single error correct, double error detect. When an uncorrectable error is found, the diagnostic attempts to reduce it to a I-bit error. This is done either by reconfiguring the memory to distribute failing bits across different ECC words or by replacing the failing chip with a spare. The result is that memory cards that previously had to be replaced can now continue to function. Thus, the life of memory cards can be prolonged. The diagnostic can also perform preventive maintenance when run in an alternate mode. In this mode, all combinations of the memory are tested to determine if there is reserve. Reserve is defined as: 1) The capability of reconfiguring the card to obtain another functional state of memory (in addition to the current operational state), or 2) The availability of functional spare chips that have not been used. Preventive maintenance is by replacing cards that have no reserve. Then, memory operation can continue error free.     

Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking

This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the $hbox{tt QCADesigner}$ simulator are performed to verify the functionality of the proposed QCA memory cell.      

High-density static ESFI MOS memory cells

The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 /spl mu/m/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells known so far. The static and dynamic behavior of these cells are discussed, as well as their behavior in a large-scale integrated (LSI) circuit; for this purpose an exploratory memory with 4096 bits and with simple decoding and sensing circuitry has been realized on an area of 3.5/spl times/4.2 mm (140/spl times/170 mils). Taking into account the measured data, an ESFI MOS memory circuit shows a better performance in speed and power dissipation than dynamic MOS memories, but its principal advantage is the static operation mode.     

The capacity of the Kanerva associative memory

Asymptotic expressions for the capacity of an associative memory proposed by P. Kanerva (1984) are derived. Capacity is defined as the maximum number of random binary words that can be stored at random addresses so that the probability that a word is in error is arbitrarily small when it is retrieved by an n-bit address containing fewer than δn errors, δ⩽1/2. Sphere-packing arguments show that the capacity of any associative memory can grow exponentially in n at a rate of at most 1-h₂(δ), where h₂(δ) is the binary entropy function in bits. It turns out that the Kanerva associative memory achieves this upper bound when its parameters are optimally set. Thus, the capacity of the Kanerva associative memory has an exponential growth rate equal to the rate of the best information-theoretic codes, that is 1-h ₂(δ). However, the Kanerva memory achieves its exponential growth in capacity at the expense of an exponential growth in hardware     

基于哈希表的高效存储器内建自修复方法

 现有存储器内建自修复方法要么遍历式地址比较效率低,要么并行地址比较功耗高,都不适用于大故障数存储器.对此,本文提出一种高效的存储器内建自修复方法,该方法对占故障主体的单元故障地址以哈希表形式进行存储,以利用哈希表的快速搜索特性提升地址比较效率.本文方法修复后的存储器在1个时钟周期内即可完成地址比较,修复后存储器性能不受任何影响,与目前广泛采用的基于CAM的方法处于同一水平,但功耗方面却具有明显优势.计算机模拟实验表明,对于512×512×8bits的存储器在同等冗余开销的情况下本文方法修复率相对于ESP方法平均提高了32.25%.     

A Highly Reliable Memory Subsystem Design Employing SECDED, Column Sparing, and Paging

This paper develops a reliability model for a paged memory system wherein the pages of memory are physically distributed among several arrays of memory chips. Any of the available pages can be used to satisfy the required memory capacity. This paper also develops a reliability model for a page or block of memory words imbedded in an array. The model assumes that memory chips have failure modes that are catastrophic to a row, to a column, to the whole physical array, or to individual bits. Spare columns or data lines are used to enhance reliability. SECDED (Single Error Correction, Double Error Detection) provides the hard-fault detection mechanism and complete fault coverage for soft faults such as 1-bit upsets. A highly reliable memory system design is described that implements a paging scheme, uses a SECDED code for hard fault detection and isolation, and uses three levels of sparing to recover from failures. The significance of this paper is that it considers failure modes associated with interfacing a memory chip into an array of memory chips. These failure modes have an impact beyond the boundaries of an individual chip; they affect the entire physical array and must be considered in the reliability model. When this is done the reliability model permits trading off page size and array size with reliability.     

Contactless read-out of printed memory

Contactless read-out of inkjet printed programmable memory is demonstrated. The memory is arranged as a conducting comb pattern consisting of parallel lines adjacent to a common electrode. The information content of the memory is stored in memory bits, which modulate the electrical surface-area of the lines. The data is read-out capacitively by sweeping the tip of a printed circuit board over the memory. The memory bits were printed using silver nanoparticle ink and switched from an initial, high-resistance state to a low-resistance state using rapid electrical sintering, and furthermore, from the low-resistance state to an open-circuit state via fuse-like action. This read-out approach offers potential for low-cost memory applications as well as e.g. resistance-change sensors.     

Program schemes for multilevel flash memories

This paper presents a synthetic overview of multilevel (ML) flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler-Nordheim tunneling (FNT) are discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absorption, with positive effects on the degree of parallelism and program throughput. As for FNT, much faster programming than that commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability.     

一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.     

An 80-Nanosecond plated-wire store for a time-compression multiplex transmission system

A 12-MHz 6500-bit plated-wire memory system is described and properties discussed that show feasibility for application in a time-compression multiplex analog transmission system. The requirements for an assumed ten-channel time-compression multiplex system (TCM) are that 720 words of 9 bits each be written sequentially at a 12-MHz rate and the 720 words be read out at the same rate but in a different sequence. This process of serial write and serial read is continuous as coded samples are taken from each of the ten input channels. The important properties of the memory system described in detail are the generation and steering of the one-ampere word current of 30-ns duration, the effect of the short- duration word current on memory write, and the signal-to-noise ratio achieved using beam-lead diode matrix word selection and beam-lead tantalum film digit detectors.     

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.