Safety analysis of mechatronic product lines

Most methodologies for the design and analysis of mechatronic systems target a single product. From a business perspective, successful product development requires shortening development times, reducing engineering costs and offering a greater variety of product options for customers. In software engineering, the software product line (SPL) technology has been developed to meet these conflicting goals, and several major companies have reported success stories resulting from SPL adoption. In mechanical engineering, similar methodologies have been developed under the name of product platforms. Methodologies for analyzing product qualities such as safety or reliability have been introduced for both SPL and product platforms. The problem with these methodologies is that they consider either software or mechanical product design, so they do not guide developers to find the best balance between the controller and the equipment to be controlled. Several system properties of a mechatronic product line should be investigated with mechatronic analysis methodologies before the development process branches to software, electronic and mechanical design. In particular, safety is one system property that can only be analyzed by considering both the equipment and its controller, so mechatronic methodologies early in the design are advantageous for discovering safety-related design constraints before costly design commitments are made. This paper extends the Functional Failure Identification and Propagation (FFIP) framework to the safety analysis of a mechatronic product line with options in software signal connections and equipment. The result of applying FFIP is that unsafe combinations of options are removed from the product line.     

Synthesis of modular mechatronic products: a testabilityperspective

Producing modular products that combine modules with the consideration of product performance, e.g., testability of electronic systems, is frequently stated as a design goal. However, most of mechatronic frameworks (models) discussed in the literature do not consider testability of electronic subsystems of mechatronic products. This paper assumes that the product modules have been established, and aims at the development of modular mechatronic products with the consideration of testability of electronic subsystems as a performance criterion. The generation of modular products and module testability issues are discussed. Testability points, testability values, and access paths for a module/system are crucial to the generation of modular mechatronic products. A generalized label-correcting algorithm is developed to determine the points of focus, testability values, and access paths in modules     

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.     

Model based fault detection of vehicle suspension and hydraulic brake systems

In modern vehicles, mechatronic systems are increasingly used. To improve reliability, safety and economy, an early recognition of small or drifting faults is becoming increasingly important. After a short introduction to methods of model based fault detection and diagnosis, application examples for fault detection of automotive vehicle suspension and hydraulic brake systems are given.     

A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits

The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.     

System-Based and Concurrent Design of a Smart Mechatronic System Using the Concept of Mechatronic Design Quotient (MDQ)

A mechatronic system needs an integrated, concurrent, and system-based design approach due to the existence of interactions among its subsystems, and also the existence of interactions between the criteria involved in a realistic evaluation of a mechatronic product. This paper presents a systematic methodology for a detailed mechatronic design based on a mechatronic design quotient (MDQ). MDQ is a multicriteria index, reflecting a system-based evaluation of a mechatronic design, which is calculated using soft computing techniques, thereby accommodating interactions between criteria and human experience. A niching genetic algorithm is utilized to explore the huge search space raised due to concurrent and integrated design approach, with the aim to find the elite representatives of different possible configurations. To demonstrate the method, it is applied to an industrial fish cutting machine called the Iron Butcher-an electromechanical system that falls into the class of mixed or multidomain systems.     

Telescopes as mechatronic systems

The system design of telescopes is usually dominated by the aspects of the optics and receiving instruments. The telescope structure, mechanism, and control are "only" aids to position these elements toward the celestial target, but their quality has a big impact on the final performance. This paper describes an integrated design approach to these "mechatronic" telescope subsystems.     

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

MIMO satellite communication with accelerated dual paths asynchronous design

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.     

How future automotive functional safety requirements will impact microprocessors design

Safety is one of the key issues of future automobile development. Car maker as well as suppliers need to prove that, despite increasing complexity, their electronic systems will deliver the required functionality safely and reliably. Future development and integration of these functionalities will even strengthen the need of safe system development processes and the possibility to provide evidence that all reasonable safety objectives are satisfied. Obviously with the trend of increasing complexity, there are increasing risks from systematic failures and random hardware faults that could impact negatively on vehicle safety. Safety relevant systems (such as advanced driving assistance and vehicle dynamic control units) require microcontrollers able to guarantee safety and availability with an acceptable cost. Safety must be achieved with respect to both systematic and hardware random faults, including soft-errors and common-cause failures. To provide availability, efficient and fast fault detection mechanisms shall be combined with infrastructures able to collect error events with enough details to allow reactions by the remaining hardware and the operating system. Costs shall be minimized by introducing as much robustness as needed and not more: this shall be done by avoiding unnecessary redundancies and reducing at the minimum the impact on system performances, therefore maximizing the usage of the available resources. This paper will give a short introduction on main concept of functional safety and ISO/DIS 26262, underlining the impact of such requirements on microprocessors and microcontrollers design. Some examples will be given on current approaches used to answer ISO/DIS 26262 requirements.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

野战电缆故障检测仪的设计与实现

本文采用嵌入式设计方法,实现了电缆故障检测系统的自动化、集成化、便携化设计,能够完成绝缘阻值测量、电缆长度测量、回路电阻测量和故障定位等功能,可测试各种型号电缆上发生的短路、接地、接触不良等故障,用于实战有线通信和高频电缆的敷设与维护,可有效提高电缆线路故障的排除时间。     

Backlash fault detection in mechatronic system

In this paper, a fault detection and isolation model based method for backlash phenomenon is presented. The aim of this contribution is to be able to detect then distinguish the undesirable backlash from the useful one inside an electromechanical test bench. The dynamic model of the real system is derived, using the bond graph approach, motivated by the multi-energy domain of such mechatronic system. The innovation interest of the use of the bond graph tool, resides in the exploitation of one language representation for modelling and monitoring the system with presence of mechanical faults. Fault indicators are deduced from the analytical model and used to detect and isolate undesirable backlash fault, including the physical system. Simulation and experimental tests are done on electromechanical test bench which consists of a DC motor carrying a mechanical load, through a reducer part containing a backlash phenomenon.     

False-Path Removal Using Delay Fault Simulation

Some false paths are caused by redundant stuck-at faults. Removal of those stuck-at faults automatically eliminates such false paths from the circuit. However, there are other false paths that are not associated with any redundant stuck-at fault. All segments of such a false path are shared with other testable paths. We focus on the elimination of this type of false paths. We use a non-enumerative path delay fault simulator based on the path status graph (PSG) data-structure, which duplicates selected gates to separate the detected and undetected path delay faults. The expanded circuit may contain new redundant stuck-at faults, corresponding to those undetected paths that are false. This happens because the expanded circuit has some new interconnects with only false paths passing through them. Such links become the sites for redundant stuck-at faults. Removal of these redundant faults eliminates false paths. The reported results show that the quality of the result may depend on the coverage of testable paths by the vectors that are simulated. When non-enumerative path delay simulation and implication-based redundancy removal techniques are used, the present procedure of false-path elimination can be applied to very large circuits.     

Selection of test paths for solder joint intermittent connection faults under DC stimulus

The test path of solder joint intermittent connection faults under direct-current stimulus is examined in this paper. According to the physical structure of the circuit, a network model is established first. A network node is utilised to represent the test node. The path edge refers to the number of intermittent connection faults in the path. Then, the selection criteria of the test path based on the node degree index are proposed and the solder joint intermittent connection faults are covered using fewer test paths. Finally, three circuits are selected to verify the method. To test if the intermittent fault is covered by the test paths, the intermittent fault is simulated by a switch. The results show that the proposed method can detect the solder joint intermittent connection fault using fewer test paths. Additionally, the number of detection steps is greatly reduced without compromising fault coverage.     

一种故障传播感知的程序故障定位方法

针对现有的基于覆盖的程序故障定位方法不能有效解决故障传播给定位效果带来的影响,该文提出了一种基于传播感知的程序故障定位方法。该方法首先使用收集到的程序覆盖路径信息对可疑节点空间进行压缩来有效降低计算量,然后利用节点在正常执行路径和故障执行路径中出现的频率不同确定可疑空间中的每个节点的初始可疑度,接下来通过引入边传播趋势的概念确定初始可疑度最大的节点是否具有故障传播现象,最后对感知的故障传播相关节点进行可疑度修正来确定节点的最终可疑度。相关示例分析和定位实验结果表明,该故障定位方法能有效降低故障传播给定位准确性带来的影响,定位效果良好,且随着程序规模的扩大在时间开销上较其他方法有很大优势,因而具有较高的实用价值。     

Case studies of defect localization based on software-based fault diagnosis in comparison with PEMS/OBIRCH analysis

This study verifies the accuracy of failure localization by a software-based fault diagnosis technique through comparison of the failure localization by photo emission microscope (PEMS) analysis and optical beam induced resistance change (OBIRCH) analysis. To evaluate, the software-based fault diagnosis technique was applied to 14 samples of 0.18 μm-process-node products that failed mainly due to the metal line shorts. We found that this technique was able to accurately localize the failure with a high probability (85.7%). One reason, the diagnosis returned inaccurate results is the influence of the metal line short expanding to several nets in the device simultaneously due to shorts of upper and lower metal lines. The other reason is that the fail log of the failed device itself was inaccurate due to (1) the resistance value at the short point, (2) the driving force of the cells related by the shorted points, and (3) the transition timing. We determined from our study that the rank of score calculation depends more on the mismatch rate of pass patterns than on the match rate of fail patterns. When the mismatch rate of pass patterns is less than 0.04 and the score is more than 70, the software-based fault diagnosis result is reliable. Although software-based fault diagnosis is a powerful tool for failure localization, it is necessary to combine it with hardware techniques such as PEMS analysis and OBIRCH analysis to maintain the accuracy of failure localization.     

Concurrent Delay Testing in Totally Self-Checking Systems

Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.