A 20-ns 256 K×4 FIFO memory

A 256 K×4 FIFO (first-in-first-out) CMOS memory with 20-ns access time and 30-ns cycle time is described. To accomplish full static and asynchronous operation, signal synchronizer and arbiter circuits have been developed and implemented into the device. A pair of 120-word×4-bit static memories are furnished to provide 20-ns data access from the very first read cycle. The average current measured at 30-ns read/write operation and the standby current are typically 23 and 1.2 mA, respectively     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A 128 K×8 70-MHz multiport video RAM with auto registerreload and 8×4 block WRITE feature

An 80-ns 1-Mb multiport video random-access memory (VRAM) can be organized as 128 K×8 or 256 K×4. Uninterrupted serial data streams of 70 MHz are achieved by combining pipelining and interleaving techniques with an internally triggered automatic memory-to-register transfer mechanism. DRAM bandwidth is enhanced by a block WRITE feature which can write as many as four column address locations in every CAS cycle. The write-per-bit feature has been expanded by including an on-chip write-per-bit latch and an extended mode of operation to simplify its use in a wider range of systems. The VRAM is fabricated in a 1 μm CMOS technology using double-level poly/polycide, single level metal, and trench DRAM storage capacitors for high noise immunity     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

An 18-ns 1-Mbit CMOS SRAM

A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm² cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm²     

A 20 K CMOS array with 200-ps gate delay

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5-μm channel length FETs is described. The 7.5×7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128×8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware     

An in-system reprogrammable 32 K×8 CMOS flash memory

The authors describe the design and performance of a 192-mil² 256 K (32 K×8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.5 μm EPROM base technology with a one-transistor 6×6-μm² cell, the device electrically erases all cells in the array matrix in 200 ms and electrically programs at the rate of 100 μs/byte typical. The read performance is equivalent to comparable-density CMOS EPROM devices with a chip-enable access time of 110 ns at 30-mA active current consumption. A command-port interface facilitates microprocessor-controlled reprogramming capability. Device reliability has been increased over byte-alterable EEPROMs by reducing the program power supply to 12 V. Cycling endurance experiments have demonstrated that the device is capable of more than 10000 erase/program cycles     

A 3.8-ns 16 K BiCMOS SRAM

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors     

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devices

An experimental 11-ns 8 K×18 static RAM fabricated in a 1.2-μm CMOS technology with 0.5-μm channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V V_dd. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 μm² to yield a chip size of 60 mm²     

A fast 32 K/spl times/8 CMOS static RAM with address transition detection

A high-speed 256 K (32 K/spl times/8) CMOS static RAM (SRAM) is described. Precharging and equalization schemes are implemented with address-transition-detection (ATD) techniques. With a differential sensing circuitry, a 23-ns access time is achieved (at V/SUB cc/=5 V and 25/spl deg/C) for addresses and chip-select clocks. The operating current is 36 mA in the READ cycle and 28 mA in the WRITE cycle, at 10-MHz cycling frequency. A four-transistor memory cell is designed with double-polysilicon and double -metal layers to achieve high performances. Versatile redundancy schemes consisting of polysilicon laser fuses, logical circuitry, and novel enable/disable controls are designed to repair defective cells. A compensation circuit is used to optimize writing parameters for redundant columns.     

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²     

A design for high-speed low-power CMOS fully parallelcontent-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-μm 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256×54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions     

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

An 8-ns 256K ECL SRAM with CMOS memory array and battery backupcapability

The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8-μm BiCMOS process, the chip uses 117-μm ², full-CMOS, six-transistor memory cells and measures 6.5×8.15 mm². The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

A 30-μA data-retention pseudostatic RAM with virtually staticRAM mode

A 1-Mb (128K×8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 μA, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs     

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 klogic gates and on-chip test circuitry

A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-μm BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM's used as cache and control storages in mainframe computers