An Algebraic Hardware/Software Partitioning Algorithm

Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components.A critical phase of the co-design process is to decompose a program into hardware and software .This paper proposes an algebraic partitioning algorithm whose correctness is verified in program algebra.The authors inroduce a program analysis phase before program partitioning and deveop a collection of syntax-based splitting rules.The former provides the information for moving operations from software to hardware and reducing the interaction between compoents,and th latter supports a compositional approach to program partitioning.     

基于遗传和禁忌搜索混合的软硬件划分算法

针对嵌入式系统软硬件划分问题,在比较了遗传算法（GA）和禁忌搜索（TS）各自优缺点的基础上,提出采用遗传/禁忌混合算法（GATS）的策略,用遗传算法提供并行搜索的主框架,用禁忌搜索作为遗传算法的变异算子,遗传算法中变异过程解空间的搜索由禁忌搜索实现。实验结果表明,GATS具有多出发点和记忆功能强、爬山能力强的优势,能够克服GA爬山能力差、TS单点出发的弱点。最后与单纯的遗传算法和禁忌搜索算法进行对比实验,证明GATS更有优势,得到的划分结果也更优秀。     

软硬件协同设计方法的研究

论述了嵌入式系统软硬件协同设计的一般方法，结合CORSAIR、COOL和POLIS 3种有代表性的软硬件协同设计系统，对系统描述、软硬件划分、软硬件协同综合等几个主要设计步骤进行了研究与分析，并提出了新的思路和方法。     

Acceleration of software algorithms using hardware/software co-design techniques

Currently there is significant interest in the design and implementation of embedded systems where the hardware and software subsystems are developed concurrently in order to meet design constraints. We present a development environment for general-purpose systems, where the objective is to accelerate the performance of software-based applications, which are specified by C programs. Such programs may be partitioned into hardware and software subsystems — a speed-critical region of the software is implemented in an FPGA in order to provide the performance acceleration. We also discuss two versions of the underlying system hardware architecture. Practical examples are given to illustrate our approach.     

三种软硬件划分算法的比较分析

软硬件划分是嵌入式系统软硬件协同设计中的关键技术之一,如何兼顾系统的性能和成本,达到两者的最佳结合,是软硬件划分的主要问题.针对单CPU多ASICs类型的目标结构,选取了遗传算法、禁忌搜索算法和模拟退火算法等全局优化算法进行系统的软硬件划分,并对3种算法的有效性进行了比较分析.     

基于Hopfield神经网络和禁忌搜索的软/硬件功耗划分

在目前全球倡导“低碳经济”的背景下,随着嵌入式系统大量而广泛的使用,嵌入式软件功耗已成为嵌入式系统设计的一个关键因素,而软/硬件划分是嵌入式软件功耗优化的一种重要方法。首先在性能约束条件下,建立以嵌入式软件功耗为目标的软/硬件双路划分模型;然后,提出了一种基于离散Hopfield神经网络(HNN)和禁忌搜索(TS)融合的求解算法,采用离散Hopfield算法作为主算法能较快地获得可行解,使用禁忌搜索算法“禁忌”当前解而转移到目标函数的其他极小点,从而可跳出局部最优解而快速趋于全局最优解;最后,仿真实验表明,与同类算法相比,该算法不但具有搜索速度上的优势,而且求得全局最优解的概率更高。     

嵌入式系统软硬件划分方法探索

提出了克隆选择算法在软硬件划分中的应用,讨论了目标函数、系统约束、抗体编码、克隆选择和变异等问题的处理。实验结果表明该算法具有较快的收敛速度,并获得了近似最优解。     

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。     

基于软硬件协同的AFDX协议片上系统设计

在描述片上系统总体结构的基础上,详细介绍了硬件功能、软件功能及软硬件之间的接口,重点论述了基于同步调度或异步调度的调度器设计方案、基于Mealy有限状态机的虚拟链传输控制等关键技术。在EP1S40芯片上经过验证可满足航空电子全双工交换式以太网(AFDX)协议处理芯片的设计要求。     

A new parallel tabu search algorithm for the optimization of the maximum vertex weight clique problem

The efficiency of metaheuristic algorithms depends significantly on the number of fitness value evaluations performed on candidate solutions. In addition to various intelligent techniques used to obtain better results, parallelization of calculations can substantially improve the solutions in cases where the problem is NP-hard and requires many evaluations. This study proposes a new parallel tabu search method for solving the Maximum Vertex Weight Clique Problem (MVWCP) on the Non-Uniform Memory Access (NUMA) architectures using the OpenMP parallel programming paradigm. Achieving scalability in the NUMA architectures presents significant challenges due to the high complexity of their memory systems, which can lead to performance loss. However, our proposed Tabu-NUMA algorithm provides up to $18\times$ speed-up with 64 cores for ten basic problem instances in DIMACS-W and BHOSLIB-W benchmarks. And it improves the performance of the serial Multi Neighborhood Tabu Search (MN/TS) algorithm for 38 problem instances in DIMACS-W and BHOSLIB-W benchmarks. We further evaluate our algorithm on larger datasets with thousands of edges and vertices from Network Data Repository benchmark problem instances, and we report significant improvements in terms of speed up. Our results confirm that the Tabu-NUMA algorithm is among the best recent algorithms for solving MVWCP on the NUMA architectures.     

改进的二维增强贪婪软硬件划分算法

针对嵌入式系统中的单处理器和单ASIC体系结构,将软硬件划分问题抽象为MKP模型,通过扩展其边界的维数,引入二维的贪婪算法来解决软硬件划分问题。算法旨在满足硬件面积约束、功耗约束和存储空间需求约束的前提下使系统的运行时间最优,算法的时间复杂度降低到O（log n·log n）。算法基于代表功能块粒度的控制数据流图（CFG）,摒弃了传统的面向软件或硬件的方法,给出了一种新的选择初始状态的方法,该方法将关键节点映射到软件,其余的用硬件实现,因缩小了算法的搜索空间,从而进一步提高了算法的运行速度。最后进行对比实验,实验结果证明该算法在运行时间和稳定性方面均优于遗传算法和模拟算法。     

基于多性能指标的SoC软硬件划分方法研究

针对存在多种因素影响嵌入式系统综合性能的实际情况,详细分析了影响嵌入式系统性能的各项性能指标,提出了一种基于多性能指标评价的软硬件协同划分思想。利用SoC可重用的特性,将IP核复用及软件架构重用引入到软硬件划分算法当中。通过功能模块层的抽象,将复杂的嵌入式系统构成映射到数学上的DAG（Direct Acyclic Graph）之上。提出了性能指标优先级的概念,并通过在算法中加入对给定的参数数据预先处理及引入运筹学中分支定界的思想,优化了算法的求解,加快了算法的收敛速度,较之单纯的整个空间的条件遍历更优。     

Convex regularization-based hardware/software co-design for real-time enhancement of remote sensing imagery

In this paper, we address a new approach for high-resolution reconstruction and enhancement of remote sensing (RS) imagery in near-real computational time based on the aggregated hardware/software (HW/SW) co-design paradigm. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale RS image enhancement tasks via incorporating into the fixed-point iterative reconstruction/enhancement procedures the convex convergence enforcement regularization by constructing the proper projectors onto convex sets (POCS) in the solution domain. The established POCS-regularized iterative techniques are performed separately along the range and azimuth directions over the RS scene frame making an optimal use of the sparseness properties of the employed sensor system modulation format. The hardware design is oriented on employing the Xilinx Field Programmable Gate Array XC4VSX35-10ff668 and performing the image enhancement/reconstruction tasks in a computationally efficient parallel fashion that meets the near-real time imaging system requirements. Finally, we report some simulation results and discuss the implementation performance issues related to enhancement of the real-world RS imagery indicative of the significantly increased performance efficiency gained with the developed approach.

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

面向RSoC的过程级动态软硬件划分

软硬件划分作为可重构片上系统设计的重要技术手段,其结果直接影响到系统的性能。目前的软硬件划分大多只考虑从算法本身提高划分效果,忽略了划分结果的具体配置实现,导致划分效果很不理想。分析了预配置模型下的任务描述,给出了预配置调度优先级的计算方法,设计了一种预配置调度策略;针对软硬件划分与动态可重构的特点,提出并实现了一种结合预配置的软硬件划分算法,给出了一种评价软硬件划分方案优劣的方法。实验结果表明,该划分方法具有良好的划分效果。     

Low-complex dynamic programming algorithm for hardware/software partitioning

A low-complex algorithm is proposed for the hardware/software partitioning. The proposed algorithm employs dynamic programming principles while accounting for communication delays. It is shown that the time complexity of the latest algorithm has been reduced from O(n²⋅A) to O(n⋅A), without increase in space complexity, for n code fragments and hardware area A.     

一种新的遗传模拟退火算法的软硬件划分方法

针对嵌入式系统软硬件划分问题,在分析遗传算法和模拟退火算法的主要优缺点的基础上,提出了一种新的小生境技术改进的遗传模拟退火算法（NGSA）,在遗传算法中融入模拟退火思想,同时引入小生境技术,保持群体的多样性;并采用Metropolis 法则形成新群体,改善群体的质量。实验结果证明该算法具有很强的爬山能力和全局搜索能力,与遗传算法（GA）和模拟退火算法（SA）相比适应度明显提高。     

基于改进遗传算法的可重构计算任务划分

为实现可重构计算中的软硬件任务自动划分,引入了遗传算法来搜寻最优解。为解决标准遗传算法可能出现种群早熟和种群进化后期收敛速度慢的问题,使用了小生境技术来保护种群中基因的多样性。设计了能够随适应度自动改变的自适应遗传算子（杂交算子和变异算子）。对算法进行了50次随机实验,并对结果进行分析。实验表明,改进后的遗传算法搜寻到全局最优任务划分的概率和搜寻到最优任务划分时的进化代数都要优于标准遗传算法。     

PProto: An environment for prototyping parallel programs

This paper describes Parallel Proto (PProto), an integrated environment for constructing prototypes of parallel programs. Using functional and performance modeling of dataflow specifications, PProto assists in analysis of high-level software and hardware architectural tradeoffs. Facilities provided by PProto include a visual language and an editor for describing hierarchical dataflow graphs, a resource modeling tool for creating parallel architectures, mechanisms for mapping software components to hardware components, an interactive simulator for prototype interpretation, and a reuse capability. The simulator contains components for instrumenting, animating, debugging, and displaying results of functional and performance models. The Pproto environment is built on top of a substrate for managing user interfaces and database objects to provide consistent views of design objects across system tools.