A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8-μm BiCMOS and triple-level-metallization technology, has a 15.5-mm×13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply     

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design     

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP)ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply     

A 54-MHz CMOS programmable video signal processor for HDTVapplications

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency     

A 300-MHz BiCMOS serial data transceiver

A BiCMOS circuit for serial data communication is presented. The chip has phase-locked loops for transmit frequency synthesis and receive clock recovery, serial-to-parallel and parallel-to-serial converters, and encode and decode functions. Since this is a mixed-analog/digital design, and the transmitter and receiver operate asynchronously, many techniques are used to decrease noise coupling. A 1.2 μm BiCMOS process allows operation at speeds of 300 MHz along with this high level of system integration, and the chip consumes less than 1 W from a single 5 V supply     

A 27-MHz digital-to-analog video processor

The authors describe a circuit intended for the restitution of a digital video signal into its analog red, green, and blue components. Sampling parameters according to CCIR recommendation 601 have been adopted for the digital interface. The circuit consists mainly of a complex digital processing part and three digital-to-analog converters. All of these functions have been implemented in a 38-mm² CMOS chip. The design goal was achieved by the development of an efficient 2-μm CMOS technology dedicated to analog and digital applications     

A 300-MPOS video signal processor with a parallel architecture

A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8-μm BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm×15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs     

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-μm BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW     

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW     

A 300-MHz 64-b quad-issue CMOS RISC microprocessor

This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm×18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 μm, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency     

A CMOS facsimile video signal processor

A CMOS image scanning signal processor which can be used for CCITT Group-4 facsimile has been developed. To obtain high-speed processing (5 MHz) and high-precision shading distortion correction (up to 70%), hybrid architecture of digital and analog techniques and parameter setting by software are combined. Image sensor and printer interfaces and a digital processor which can do linear zooming and data format conversion are built into a chip. The 6.5/spl times/7.8-mm chip is fabricated using 2.5 /spl mu/m CMOS technology and contains 25000 transistors.     

A mixed-signal BiCMOS front-end signal processor for high-temperature applications

A mixed-signal ASIC that implements an ultrasound front-end receiver in a 0.6 /spl mu/m BiCMOS HotASIC technology that features metal/metal capacitors and poly1/poly2 resistors is described. The ASIC includes a low-noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), and a second-order sigma-delta modulator (SDM), and is the most compact system for high-temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200 kHz to 700 kHz) from an ultrasound transducer. At 48 MHz clock frequency and 200/spl deg/C, the power consumption is 85 mW from a single 5 V supply. The die area of the chip is 5.52 mm/sup 2/.     

A 10-b 300-MHz interpolated-parallel A/D converter

A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm×4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors     

A 300-MHz 115-W 32-b bipolar ECL microprocessor

A full-custom single-chip bipolar ECL RISC microprocessor was implemented in a 1.0-μm single-poly bipolar technology. This research prototype contains a CPU and on-chip 2-KB instruction and 2-KB data caches. Worst-case power dissipation with a nominal -5.2 V supply is 115 W. The chip has been designed for a worst-case clock frequency of 275 MHz at a nominal supply. The chip verifies a new style of CAD tools developed during the design process, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques     

A BiCMOS continuous-time filter for video signal processingapplications

A fully integrated BiCMOS continuous-time filter for video signal processing applications is presented. It incorporates an input clamping circuit, a third-order equalizer, a fifth-order elliptic filter with sinx/x correction, and a 75-Ω driver. The architectures of the input and output amplifiers as well as the filter and the equalizer are chosen based on the extensive study of circuit structures and Monte Carlo simulation to meet the linearity requirement for the broadcast-quality video system. The complete chip achieves a low-pass filter response with a 5.5-MHz cutoff frequency (f_cc), 0.3-dB passband ripple, 20-ns group delay variation up to 0.9 f_c, and 43-dB attenuation at 1.45 f_c. With a nominal 2-Vpp signal at the output, measured results show 0.2% differential gain, 0.38° differential phase, and 1.7-mV rms noise demonstrating 10-bit linearity in a 1.5-μm 4-GHz BiCMOS process technology. The filter active area is 8 mm² and it dissipates 350 mW in a single 5-V power supply     

A 200-MHz IF BiCMOS signal component separator for linear LINCtransmitters

The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 μm BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a π/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter     

A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocelllibrary

A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm² die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz