PAL可编程逻辑器件开发和应用

PAL器件内含标准方式连接的逻辑门阵列,主要由可编程的“与”阵列和固定的“或”阵列、可编程的输入/输出和带有反馈的寄存器构成。用户可根据实际应用要求,用编程器通过一块接口卡与PC机接口,以PC机作为控制机,通过编程熔断或保留PAL器件内的熔丝,而产生特定的逻辑功能。     

A set of four ICs in CMOS technology for a programmable hearing aid

A four-chip system developed for a programmable hearing aid is presented. It combines E²PROM (electrically erasable programmable read-only memory) memories with a control logic, low-noise preamplifiers, AGC (automatic gain control) amplifiers, SC (switched-capacitor) filters, voltage multipliers, and an output amplifier of the pulse-width type. The implementation of the critical parts is explained. The 3-μm self-aligned-contacts MOS technology of the Faselec company is used. The system is supplied by a single 1.3-V battery and its typical current consumption is 1.5 mA. The whole system can be connected to a computer     

一种用于千兆以太网的高增益、宽带限幅放大器

设计了一种高增益、宽带限幅放大器,最大速率为1.25Gb/s。限幅放大器包括多级放大级、输出驱动级、失调消除和信号检测电路,提供固定的正参考发射机耦合逻辑(PECL)输出电平,且可通过编程设定信号丢失(LOS)指示。当输入信号降低到设定门限时关闭输出以达到静噪之目的。放大器采用3.3V单一电源,采用TSMC0.35μmBiCMOS工艺设计版图,放大器版图面积为1.3mm×1.1mm。测试结果显示,在3.3V电源下具有超过52dB的动态范围,功耗仅60mW。     

A 288K CMOS EPROM with redundancy

A 150 ns 288K CMOS EPROM with a nine-block cell array and a standby current of less than 1 /spl mu/A has been developed. This device can be used as an 8 or 9-bit EPROM. The ninth block can be used as a redundant block by electrically programmable polysilicon fuses. A redundant row decoder is also included. Improvements in the lithography and process technologies have reduced the cell size to 9 /spl times/ 6 /spl mu/m and the chip size to 7.44 /spl times/ 4.65 mm.     

基于FPGA的简易数字存储示波器设计

主要以简易数字存储示波器为例,介绍可编程逻辑器件在模数转换、数模转换及数据存储与处理中的设计方法。此系统由四部分组成,其中数据处理及存储单元用VHDL语言进行设计,利用MAX＋PLUSII软件进行电路仿真,并选用FP6A硬件实现;输入单元及输出单元采用AD976及AD669芯片实现;存储器RAM采用HM6264芯片实现。设计中采用了白顶向下的方法,将系统按逻辑功能划分模块,各模块使用VHDL语言进行设计,在ISE中完成软件的设计和仿真。     

A 1.5-GHz programmable divide-by-N GaAs counter

A GaAs divide-by-N programmable counter has been fabricated for use in microwave frequency synthesizers and other applications. The counter uses a 1-μm depletion-mode MESFET process. The counter is typically capable of dividing an input frequency of DC to 1.5 GHz by any divisor from 3 to 64 over a temperature range of -60 to 100°C. Input and output translators are incorporated to render the device fully compatible with emitter-coupled logic (ECL) logic levels. Power dissipation for the chip is 1.4 W. A custom gigahertz-rate automated digital IC tester has been used to characterize the counter. Reliability data to date indicate a minimum mean time to failure (MTTF) of 1.8×10⁶ h at 100°C     

An 8K/spl times/8 dynamic RAM with self-refresh

The device uses a standard NMOS one-transistor cell and is fabricated with a double polysilicon HMOS technology using polysilicon word lines and folded metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, and refresh counter. A high-speed arbiter resolves conflicts between refresh cycles and memory accesses. A `ready' output is provided to the processor. A multiplexed bus is provided in the array to carry column addresses and also I/O data paths. Another multiplexed bus is used for data lines between the input buffers, write buffers, secondary sense amplifiers, and output buffers. Redundant rows and columns are used for increased manufacturing yield. Polysilicon fuses are electrically programmed to select redundant elements.     

A high-speed mixed digital-to-analog circuit board for accuratecontrol of wavelength tunable lasers for fiber-optic communications

A mixed digital-to-analog (D/A) high speed circuit board capable of driving a tunable super structure grating distributed Bragg reflector (DBR) laser is developed. The circuit is used to control the laser over a 20-nm tuning wavelength range with 0.1 nm resolution. Three control currents are preprogrammed into an electrically erasable/programmable read-only memory (EEPROM) look-up table for each wavelength. Upon receiving a differential logic control signal, the circuit tunes the laser to the specified output wavelength within 500 ns. The long-term repeatability of the tuned laser output wavelength shows drift below ±0.02 nm with greater than 100 h of operation     

直管内壁TIG/CO_2自动堆焊机控制装置

介绍了可编程序控制器硬件输入输出控制电路及软件程序流程图,通过PLC控制TIG/CO2堆焊机对多种规格金属直管及容器内壁堆焊金属材料,使金属直管及容器具有耐腐蚀,强度高等性能,在石油化工等行业有着较广泛的应用.     

直管内壁TIG／CO2自动堆焊机控制装置

介绍了可编程序控制器硬件输入输出控制电路及软件程序流程图,通过PLC控制TIG／CO2堆焊机对多种规格金属直管及容器内壁堆焊金属材料,使金属直管及容器具有耐腐蚀,强度高等性能,在石油化工等行业有着较广泛的应用。     

一种FPGA新型逻辑单元结构的设计

提出了一种FPGA可编程逻辑单元的新结构,该结构具有较多的输入端数和输出端数,并加入了专用的快速进位逻辑、专用级联链等功能,使得这种结构可用来实现任意4输入的逻辑函数和某些高达11个变量的输入函数;这种结构还可同时实现两个任意3输入的逻辑函数或最多5输入的某些函数,而且也能实现快速的进位计算和高扇入的逻辑运算.与目前一些商业FPGA的逻辑结构进行比较表明,本文提出的单元结构不仅具有较高的资源利用率,而且在性能和函数实现能力上都有较大的优势.     

SW3424电源电压监控保护电路的设计与应用

本文介绍并分析了一种电源电压监控保护电路的工作原理及应用。该保护电路采用了双通道输入／双通运输出。输入比较器有较宽的共模电压范围，有可编程磁滞输入和可编程输入／输出延时。输出采用了大电流驱动输出和显示输出。本文给出了其主要性能指标、典型应用连接图及需注意的问题。该电路可广泛用于航空、航天、雷达、通信及精密仪器等领域。     

一种宽分频范围的CMOS可编程分频器设计

设计了一种基于双模预分频的宽范围可编程分频器。对预分频器的逻辑电路进行了改进,提高了最高工作频率,同时,引入输入缓冲级,增加了低频时分频器的输入敏感性。基于Chartered 0.25μm厚栅CMOS工艺,在SpectreRF中仿真,分频器可在50MHz～2.2GHz频率范围正常工作。流片测试结果表明,该分频器可正常工作在作为数字电视调谐芯片本振源的PLL中,对80～900MHz的VCO输出信号,实现256～32767连续分频。     

Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices

The circuit concept of programmable logic gates based on the controlled quenching of series-connected negative differential resistance (NDR) devices is introduced, along with the detailed logic synthesis and circuit modeling. At the rising edge of a clocked supply voltage, the NDR devices are quenched in the ascending order of peak currents that can be reordered by the control gates and input gates biases, thus, providing programmable logic functions. The simulated results agree well with the experimental demonstration of the programmable logic gate fabricated by a monolithic integrated resonant tunneling diode/high electron mobility transistor technology.     

Multiterminal light-emitting logic device electricallyreprogrammable between OR and NAND functions

A monolithic multiterminal logic device that functions both optically and electrically as an ORNAND gate, is demonstrated for the first time. The device, based on the real-space transfer of hot electrons into a complementary collector layer, has been implemented in an InGaAs/InAlAs/InGaAs heterostructure grown by molecular beam epitaxy. Excellent performance is obtained at room temperature. The collector current and the optical output power both exhibit the OR and the NAND functions of any two of the three input terminals, these functions being interchangeable by the voltage on the third terminal     

Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller

A novel analog integrated circuit implementation of an adaptive fuzzy logic controller (AFLC), called variable universe fuzzy logic controller (VFLC), is presented which has not been reported before. The VFLC is a stable controller which has fewer on-line adapting parameters than the conventional AFLCs based on adapting fuzzy rules, thus it is more suitable for hardware implementation. The input and output universes of discourse of the VFLC are adaptively changed according to the input variables to improve the control effect. A novel peaky-triangle membership function is presented to realize the complex input universe variation. The absolute value of the integral of the input variables is used for the output universe variation, and then it is multiplied with the output of the conventional fuzzy logic controller to form the final output. The other parts are minimization circuits and a center of gravity defuzzification circuit that does not use a division circuit. An analog VFLC with 2 inputs, 1 output, and 9 rules is designed and fabricated using a 0.6-$mu$ m CMOS standard technology. It can work either in a non-adaptive or an adaptive mode. The measurements show that it completes the VFLC functions.      

A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.     

A high-speed digitally programmable CCD transversal filter

A 32-stage programmable transversal filter is described which has 6-bit digitally programmable tap weights and has been operated at a 25-MHz clock rate. The device has a linear dynamic range of more than 60 dB and occupies a chip area of 24 mm/SUP 2/. Pipe-organ architecture made it possible to use a simple floating diffusion output circuit. The tap weight values are set by a 6-bit multiplying D/A converter (MDAC) at each delay-line input. The MDAC is a multiple CCD input structure with binary-weighted input gate areas and logic-controlled gates to multiply each charge packet by 0 or 1. The conversion speed of this structure is as high as that of a CCD input structure, but careful control of threshold voltage variations is required to achieve high accuracy. Experiments are described which show that threshold offsets can be reduced to about 2 mV RMS for a fill-and-spill input indicating that MDACs of this type with 8-bit accuracy are feasible.     

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.