Semi‐blind fast equalization of QAM channels using concurrent gradient‐Newton CMA and soft decision‐directed scheme

This contribution considers semi‐blind adaptive equalization for communication systems that employ high‐throughput quadrature amplitude modulation signalling. A minimum number of training symbols, approximately equal to the dimension of the equalizer, are first utilized to provide a rough initial least‐squares estimate of the equalizer's weight vector. A novel gradient‐Newton concurrent constant modulus algorithm and soft decision‐directed scheme are then applied to adapt the equalizer. The proposed semi‐blind adaptive algorithm is capable of converging fast and accurately to the optimal minimum mean‐square error equalization solution. Simulation results obtained demonstrate that the convergence speed of this semi‐blind adaptive algorithm is close to that of the training‐based recursive least‐square algorithm. Copyright © 2009 John Wiley & Sons, Ltd.     

π／4 DQPSK解调算法的研究与仿真

针对数字通信系统中符号间干扰（ISI）问题,提出了一种适用于π／4 DQPSK解调的自适应盲均衡和载波恢复算法。T／4 CMA盲均衡器利用接收信号的所有采样点进行迭代,解决了采样相位敏感的问题;改进的载波恢复算法简单易于实现,减小了接收机设计的复杂度和难度。仿真结果表明,这种算法复杂度小、性能好,具有一定的实用价值。     

一种MMSE类盲均衡算法的凸组合策略

通常有2类重要的MMSE类盲均衡算法：恒模盲均衡算法和判决引导算法。前者面临收敛速度慢,剩余误差大的缺点;而判决引导均衡算法的收敛速度快,稳态性能好,缺点是启动条件不满足时算法会发散。本论文提出了一种MMSE类盲均衡算法的凸组合策略。通过应用凸组合的基本原理,恒模盲均衡算法可以自适应平滑地切换到判决引导模式。首先,提出了算法的凸组合策略,使得恒模盲均衡算法和判决引导算法之间可以自动软切换。然后描述了一种锚定过程,可以消除稳态时恒模均衡器过高的剩余误差,因此总的算法可以看作是经过了恒模均衡器训练的判决引导均衡。仿真实验证实了新算法的优异性能。     

Blind decoder‐assisted interference reduction for coded DS‐CDMA systems

We propose an iterative blind interference reduction strategy for short‐burst coded DS‐CDMA systems. The blind strategy works by creating a set of ‘training sequences’ in the receiver that are used as input to an interference reduction algorithm whose task is to produce a corresponding set of equalizers that attempt to recover the desired signal. To maintain a reasonable complexity level we develop a semi‐blind interference reduction algorithm that is capable of equalizing the received signal with a relatively small training sequence length (thus maintaining a small training sequence set). The objective then becomes to determine which equalizer from the generated set gives the best performance (smallest bit error). It is demonstrated that the success of this scheme depends greatly on the ability to find an appropriate criterion for picking the best equalizer. Of the tested criteria, one based on feedback from the decoder (essentially using trellis information) is shown to achieve nearly optimal performance. Copyright © 2005 John Wiley & Sons, Ltd.     

Double‐Switch Series‐Resonant Cell‐Voltage Equalizer Using a Voltage Multiplier for Series‐Connected Energy Storage Cells

Series connections of energy storage cells, such as lithium‐ion cells and electric double‐layer capacitors (EDLCs), require cell‐voltage equalizers to ensure years of operation. Conventional equalizers require multiple switches, magnetic components, and/or secondary windings of a multiwinding transformer in proportion to the number of series connections, which usually makes them complex, expensive, bulky, and less extendable with increasing series connections. A double‐switch series‐resonant equalizer using a voltage multiplier is proposed in this paper. The double‐switch operation without a multiwinding transformer achieves simplified circuitry and good modularity at reduced size and cost, compared to conventional equalizers. Operational analyses were separately performed for the following two functional parts of the proposed equalizer: a series‐resonant inverter and a voltage multiplier. The mathematical analyses derived a dc‐equivalent circuit of the proposed equalizer, with which simulation analyses of even an hour's duration can be completed in an instant. Simulation analyses were separately performed for both the original and equivalent circuits. The simulation results of the derived circuit correlated well with those of the original circuit, thus verifying the derived dc‐equivalent circuit. A 5‐W prototype of the proposed equalizer was built for eight cells connected in series and an experimental equalization was performed for series‐connected EDLCs from an initially voltage‐imbalanced condition. The voltage imbalance was gradually eliminated over time, and the standard deviation in the cell voltages decreased to approximately 5 mV at the end of the experiment, thus demonstrating the equalization performance of the proposed equalizer.     

An improved decision feedback equalization using a priori information

This paper addresses the exhaustive computational complexity of the maximum‐a‐posteriori equalizer and the inefficiency of the conventional decision feedback equalizer (DFE) algorithm in iterative equalization, especially when the higher‐level modulation is used with severely distorted Inter Symbol Interference channels. The new method proposed here improves the bit error rate (BER) performance by computing the extra metric r_n+1 using the feedback symbols from previous iteration and combining it with a priori information of the symbols. After each iteration, the hard‐detected symbols are saved in the memory as a priori data for next iteration. We verified the proposed algorithm for Binary Phase Shift Keying and 8‐phase shift keying modulation. The promising simulation results show that the BER performance given by the proposed low complexity DFE algorithm improved dramatically throughout the iterations when the conventional DFE has only insignificant improvement in the process of iterative equalization. Copyright © 2009 John Wiley & Sons, Ltd.     

Electric double‐layer capacitor module with series‐parallel reconfigurable cell voltage equalizers

When electric double‐layer capacitors (EDLCs) are connected in series, a cell voltage imbalance occurs due to nonuniform cell properties. Cell voltage imbalance should be minimized to prolong cycle lives and maximize the available energy of cells. In this study, we propose a series‐parallel reconfigurable cell voltage equalizer that is considered suitable for energy storage systems using EDLCs instead of traditional secondary batteries as the main energy storage sources. The proposed equalizer requires only EDLCs and switches as its main circuit elements, and it utilizes EDLCs not only for energy storage but also for equalization. An equivalent circuit model using equivalent resistors that can be regarded as an index of equalization speed is developed. Current distribution and cell voltage imbalancing during operation are quantitatively generalized. Experimental charge–discharge tests were performed on the EDLC modules to demonstrate the performance of the cell voltage equalizer. All the cells in the modules could be charged/discharged uniformly even when a degradation‐mimicking cell was intentionally included in the module. The resultant cell voltage imbalances and current distributions were in good agreement with those predicted by mathematical analyses. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(4): 38–50, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21287     

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley & Sons, Ltd.     

Compact self‐constructing recurrent fuzzy neural network with decision feedback for quadrature amplitude modulation signaling systems

This paper proposes a novel adaptive decision feedback equalizer (DFE) based on compact self‐constructing recurrent fuzzy neural network (CSRFNN) for quadrature amplitude modulation systems. Without the prior knowledge of channel characteristics, a novel training scheme containing both compact self‐constructing learning (CSL) and real‐time recurrent learning algorithms is derived for the CSRFNN. The proposed CSL algorithm adopts two evaluation criteria to intelligently decide the number of fuzzy rules that are necessary. The real‐time recurrent learning is performed simultaneously with the CSL at each time instant to adjust DFE parameters. The proposed DFE is compared with several neural network‐based DFEs on a nonlinear complex‐valued channel. The results show that the CSRFNN DFE is superior to classical neural network DFEs in terms of symbol‐error rate, convergence speed, and time cost. Copyright © 2011 John Wiley & Sons, Ltd.     

The performance analyses of multitarget CMA adaptive array considering mutual coupling and diffraction effects

The performance of a multitarget constant modulus algorithm (MU‐CMA) adaptive array located on a regular conducting plate is studied in this paper. The effects of mutual coupling (MC) between array elements and diffraction caused by the conducting plate are taken into account. A hybrid method of equivalent edge current method (ECM) and moment method (MM) is employed in electromagnetic calculation to investigate the distortion of initial array pattern. We compare the capture property of three well‐known MU‐CMA arrays, respectively: multitarget least‐squares constant modulus array (MT‐LSCMA), multitarget decision‐directed array (MT‐DD) and least‐squares despread respread multitarget constant modulus array (LS‐DRMTCMA). Simulation result shows that: (i) the distorted initial pattern leads to the descending of the signal catch performance of MT‐LSCMA and MT‐DD; (ii) only the LS‐DRMTCMA can work correctly due to its stronger anti‐jamming ability in the presence of MC and diffraction. Copyright © 2006 John Wiley & Sons, Ltd.     

Optimal delay estimation and performance evaluation in blind equalization

This paper deals with the problem of recovering the input signal applied to a linear time-invariant system from the measurements of its output and the a priori knowledge of the input statistics (blind equalization). Under the assumption of an i.i.d. non-Gaussian input sequence a new iterative procedure based on phase-sensitive high-order cumulants for adjusting the coefficients of a transversal equalizer is introduced. The main feature of the proposed technique is the automatic selection of the equalization delay so as to improve the equalization performance. A method for the a posteriori evaluation of the obtained accuracy in PAM systems is also introduced. It consists of the computation of an upper bound on the probability of error depending on certain moments of the equalizer output and the statistics of the channel input and therefore can be used in a blind equalization context. Based on the result of such a computation, it can be decided whether it is necessary to consider a longer equalization filter in the iterative procedure. © 1997 John Wiley & Sons, Ltd.     

Fractionally spaced spatial adaptive equalization of S‐UMTS mobile terminals

In this paper we present fractionally spaced adaptive equalization techniques and space diversity combined receiver and evaluate their performance for the downlink of S‐UMTS system. The conventional ‘training’ (or non‐blind) and the ‘unsupervised’ (or blind) adaptive equalization algorithms are both investigated. Simulation results show that the equalizers are robust to Doppler shift and non‐linearity effects due to TWT amplifiers aboard the satellite. It is also shown that even with a moderate array size of two antenna elements, a significant improvement in terminal performance is achieved. Copyright © 2002 John Wiley & Sons, Ltd.     

高阶QAM实时多域测试多模式自适应盲均衡技术研究

提出了一种全新的宽带通信信号实时多域分析通用架构,详细介绍了该架构下信号分析的基本原理。在这种架构的基础上,通过加载不同的算法,不仅能够实现各种宽带通信信号高精度实时宽带频谱分析,而且还能同时实现宽带通信信号时域、调制域等多域联合分析。针对宽带高阶正交幅度调制（QAM）通信信号实时多域分析,详细讨论了面向测试的基于GMMA和DDLMS双模自适应盲均衡算法。系统仿真结果证明：相比GMMA自适应盲均衡算法,双模自适应盲均衡算法收敛速度明显提高,256QAM信号均衡后输出残余码间串扰（ISI）改善提高了10dB;同时通过实验验证,采用20MHz实时分析带宽对码率为6.4MSps的宽带256QAM信号进行实时多域分析,误差矢量幅度（error vectorm agnitude,EVM）测试误差小于2%。     

A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process

For a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm² including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.     

Zero‐voltage switching modular equalization system for series super‐capacitor string

This paper presents a zero‐voltage‐switching modular equalization for series super‐capacitor string in a large energy storage system. The zero‐voltage working scheme is analyzed based on Power Simulation (PSIM) to verify its validity. An equalization system test for 16‐super‐capacitor cells is conducted under voltage‐imbalanced conditions. The power flow model, switching patterns, and zero‐voltage gap are discussed. The simulation and experimental results are presented, indicating that the equalization not only inherits the advantages of traditional inductor‐based super‐capacitor equalization system, but also brings some merits, such as flexible, low switching loss, and highly modularized.     

A genetic‐based neuro‐fuzzy controller for blind equalization of time‐varying channels

This paper presents a neuro‐fuzzy network (NFN) where all its parameters can be tuned simultaneously using genetic algorithms (GAs). The approach combines the merits of fuzzy logic theory, neural networks and GAs. The proposed NFN does not require a priori knowledge about the system and eliminates the need for complicated design steps such as manual tuning of input–output membership functions, and selection of fuzzy rule base. Although, only conventional GAs have been used, convergence results are very encouraging. A well‐known numerical example derived from literature is used to evaluate and compare the performance of the network with other equalizing approaches. Simulation results show that the proposed neuro‐fuzzy controller, all parameters of which have been tuned simultaneously using GAs, offers advantages over existing equalizers and has improved performance. From the perspective of application and implementation, this paper is very interesting as it provides a new method for performing blind equalization. The main contribution of this paper is the use of learning algorithms to train a feed‐forward neural network for M‐ary QAM and PSK signals. This paper also provides a platform for researchers of the area for further development. Copyright © 2008 John Wiley & Sons, Ltd.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

基于开关矩阵拓扑的蓄电池组均衡控制策略

提出一种应用于直流不间断供电系统蓄电池组单体电池均衡的桥式开关矩阵拓扑,利用LC均衡器进行能量的存储和转移,实现了能量从电池组中荷电状态(SOC)最高的单体电池向最低的单体电池转移,给出了参数设计方法,在避免迂回均衡带来蓄电池充放电次数增多的同时,延长了蓄电池的寿命,提高了均衡和能量转移效率。在Matlab-Simulink环境下搭建了均衡系统模型并进行了仿真,结果验证了所提出均衡策略的有效性和可行性。     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.