Amorphous silicon thin-film transistors on steel foil substrates

We report the successful fabrication of high-quality a-Si:H thin-film transistors (TFTs) on stainless steel foil substrates. TFTs with an inverted-staggered structure were grown on 200-μm thick stainless steel foil. These TFTs show typical ON/OFF current ratios of 10⁷, OFF currents on the order of 10^-12 A, good linear and saturation current behavior, subthreshold slopes of 0.5 V/decade, and linear channel mobilities of 0.5 cm²/V. In addition, we have demonstrated that these TFTs are capable of withstanding significant mechanical shocks, as well as macroscopic deformation of the substrate, while remaining functional. This work demonstrates that transistor circuits can be made on a flexible, nonbreakable substrate. Such circuits would be highly useful in reflective or emissive displays, and in other applications that require rugged macroelectronic circuits     

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

Stability of amorphous-silicon TFTs deposited on clear plastic substrates at 250/spl deg/C to 280/spl deg/ C

Amorphous-silicon (a-Si) thin-film transistors (TFTs) were fabricated on a free-standing new clear plastic substrate with high glass transition temperature (T/sub g/) of >315/spl deg/ C and low coefficient of thermal expansion of <10 ppm/ /spl deg/ C. Maximum process temperatures on the substrates were 250/spl deg/C and 280/spl deg/C, close to the temperatures used in industrial a-Si TFT production on glass substrates. The first TFTs made at 280/spl deg/C have dc characteristics comparable to TFTs made on glass. The stability of the 250/spl deg/C TFTs on clear plastic is approaching that of TFTs made on glass at 300/spl deg/C-350/spl deg/C. TFT characteristics and stability depend only on process temperature and not on substrate type.     

Dynamic Response of Normal and Corbino a-Si:H TFTs for AM-OLEDs

The dynamic characteristics of normal and Corbino hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) have been investigated. Top- and bottom-gate normal a-Si:H TFTs and bottom-gate Corbino a-Si:H TFTs were fabricated with a five-photomask process used in the processing of the active-matrix liquid crystal displays. The charging time and feedthrough voltage $Delta V_{P}$ measurement indicates that the normal a-Si:H TFT shows a similar behavior regardless of its TFT geometrical structure. Using a simple gate-to-source capacitance $C_{rm GS}$ model, the dependence of $Delta V_{P}$ on gate-to-source overlap and storage capacitor has closely been estimated using analytical calculation. Due to a unique electrode geometry, the Corbino a-Si:H TFT shows a small deviation from an analytical model used for the normal a-Si:H TFT, and consequently, a modified analytical model was developed. We also developed concepts of its possible application as a switching device to active-matrix organic light-emitting displays.      

Improvement of the reliability of amorphous silicon transistors byconduction-band tail width reduction

We present theoretical and experimental evidence showing that bias induced threshold voltage degradation of a-Si:H transistors is reduced by decreasing the width of the conduction-band tail. We show that transistors which are made using a thick (0.5 μm) a-Si:H layer possess a narrower conduction-band tail compared to transistors made using thin (0.05 μm) a-Si:H layers. We find that bias-induced threshold voltage degradation decreases by a factor of two for thick-layered TFTs compared with conventional, thin-layered TFTs. Finally, we present device design guidelines for improving the reliability of a-Si:H TFTs including several possible device designs for achieving further improvements in the reliability of a-Si:H TFTs     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Threshold voltage shift compensated active pixel sensor array for digital X-ray imaging in a-Si technology

A new active pixel sensor for X-ray digital imaging using amorphous silicon thin-film transistors (a-Si TFTs) is proposed. Simulation results show that this new APS structure is fully capable of compensating for variations in threshold voltage (V/sub T/) of a-Si TFTs under prolonged gate voltage stress.     

Thick-layered etched-contact amorphous silicon transistors

We introduce a new thick-layered, etched-contact a-Si:H TFT (TLEC-TFT) structure which allows the use of thick a-Si:H layers without increasing the TFT contact resistance. This device facilitates the integration of high-performance TFTs and thick-layered photo-transistors in a-Si:H-based image sensors. The TLEC-TFT is fully compatible with the conventional TFT fabrication process and requires no extra masking steps. For low values of the drain-to-source voltage, our new TFT boosts the linear region current by two orders of magnitude over that of conventional TFTs with identically thick a-Si:H layers. By removing the adverse effects of contact resistance in transistors with thick a-Si:H layers, our TLEC-TFT design allows us to compare the performance of TFTs with thick and thin a-Si:H layers. We find that the width of the conduction-band tail decreases in thick-layered a-Si:H TFTs. This reduction in the width of the band tails results in an increase in the TFT mobility and subthreshold slope. Consequently, thick-layered, etched-contact TFTs possess higher overall current-drive capabilities compared to conventional, thin-layered TFTs. We present experimental evidence which correlates the width of the conduction-band tail to the density of as-deposited free carriers     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

Planarized copper gate hydrogenated amorphous-silicon thin-filmtransistors for AM-LCDs

We report the first fabrication of inverted-staggered back-channel-etch hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a planarized Cu gate electrode. The Cu gate-planarized (GP) a-Si:H TFTs, incorporating benzocyclobutene and a-SiN_x:H as a double-layer gate insulator, had a field-effect mobility of 0.75 cm²/V-s, a threshold voltage of 4.92 V, and a subthreshold swing (S) of 0.48 V/dec. These results demonstrate that the GP-TFTs can have an electrical performance comparable with the conventional TFTs without gate planarization. Thus, the gate planarization technology is suitable for application in large-area and high-resolution active-matrix liquid-crystal displays     

High transmittance TFT-LCD panels using low-/spl kappa/ CVD films

Thin-film transistor liquid crystal display (TFT-LCD) panels of a high transmittance structure were fabricated by using a low-/spl kappa/ dielectric film as a passivation layer. The low-dielectric films were successfully deposited and patterned using a conventional plasma-enhanced chemical vapor deposition (PECVD) and plasma-assisted etching techniques. The interface between the a-Si channel and the overlaying passivation was modified by appropriate plasma treatment prior to the low-/spl kappa/ deposition. TFTs having the a-Si:C:O:H passivation showed a transfer characteristics similar to that of conventional TFTs. The high transmittance panel showed brightness approximately 30% higher than that of a standard panel without degrading other display characteristics, such as crosstalk.     

Ferroelectric liquid-crystal shutter array with a-Si:H TFT driver

A ferroelectric liquid crystal (FLC) shutter array with an a-Si:H thin-film transistor (TFT) drive, designed for a low-cost and high-performance optical printing head, is presented. The a-Si:H TFT driver consists of inverter circuits, switch TFTs, and matrix circuits. A block driving method was employed to compensate for the low operating speed of the a-Si:H TFTs. The 256-dot, 300-dot/in resolution prototype device mounted in a printing head shows an over-30 contrast ratio and an 8-page/min operating speed. Additional measurements on this device demonstrate the possibility of operation with a 24-page/min speed at a 600 dot/in resolution     

Low-Temperature Deposition of Hydrogenated Amorphous Silicon in an Electron Cyclotron Resonance Reactor for Flexible Displays

Electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECR-PECVD) is investigated as a technique for depositing hydrogenated amorphous silicon (a-Si : H) at a temperature of 80/spl deg/C, which is compatible with the use of transparent, plastic substrates. The ECR-PECVD reactor is described and the principles underlying its operation explained. In particular, the factors controlling the deposition of a-Si : H by this technique are investigated, and it is shown that control of gas phase reactions between silane and hydrogen species is essential. High-quality a-Si : H is deposited in a narrow processing window with a photosensitivity greater than 10/sup 6/. Thin-film transistors (TFTs) fabricated at 125/spl deg/C incorporating low-temperature a-Si : H as the channel layer have a switching ratio of almost 10/sup 5/. With further optimization of the other material layers, such TFTs could be used for the active matrix transistors in flexible liquid crystal displays on plastic substrates.     

Electrical Stability of Hexagonal a-Si:H TFTs

In this letter, we study the current-temperature-stress-induced electrical instability of single and multiple hexagonal (HEX) hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) connected in parallel. The influence of the threshold voltage shift of a single HEX TFT on the overall electrical performance of multiple HEX TFTs is discussed. The results indicate that a-Si:H HEX TFTs have an improved electrical stability and a threshold voltage shift linear dependence on a number of connected HEX-TFT units.     

Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of SiO2

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO₂ was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO₂ C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO₂ C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm²/Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions     

Integration and characterization of amorphous silicon thin-filmtransistor and Mo-tips for active-matrix cathodes

We have designed and monolithically integrated amorphous silicon thin-film transistor (a-Si TFT) with Mo-tip field emitter arrays (FEAs) on glass substrate for active-matrix cathodes (AMCs) in field-emission display (FED) application. In our AMCs, a light shield layer of metal was introduced to reduce the photo leakage and back channel currents of a-Si TFT. The light shield was designed to have the role of focusing grid to focus emitted electron beams from the AMC on the corresponding anode pixel by forming it around the Mo-tip FEAs as well as above the a-Si TFT. The thin film depositions in a-Si TFTs were performed at a high temperature of above 360°C to guarantee the postvacuum packaging process of cathode and anode plates in FED. Also, a novel wet etching process was developed for n⁺-doped-a-Si etching with high etch selectivity to intrinsic a-Si and good etch controllability and was used in the fabrication of inverted stagger TFT with a very thin active layer. The developed a-Si TFTs had good enough performance to be used as control devices for AMCs with Mo-tip emitters. The fabricated AMCs exhibited very effective aging process for field emitters     

A new bottom-gated poly-Si thin-film transistor

We have proposed and fabricated the new bottom-gated poly-Si TFT with a partial amorphous-Si (a-Si) region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the reverse leakage currents are decreased significantly in the new poly-Si TFT compared with conventional one. This reduction is due to the suppression of field emission currents by local a-Si region like that of a-Si TFTs while the ON currents are kept almost the same due to the considerable inducement of electron carriers in the short a-Si channel by the positive gate bias     

A maskless laser-write lithography processing of thin-film transistors on a hemispherical surface

We report on the design and fabrication methods for a hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a non-planar substrate using laser-write lithography (LWL). Level-to-level alignment with a high accuracy is demonstrated using LWL method. The fabricated a-Si:H TFT exhibits a field-effect mobility of 0.27 cm²/V s, threshold voltage of 4.9 V and on/off current ratio of ∼6 × 10⁶ in a saturation regime. The obtained results demonstrate that it is possible to fabricate the a-Si:H TFTs and complex circuitry on a curved surface, using a well-established a-Si:H TFT technology in combination with the maskless lithography, for hemispherical or non-planar sensor arrays.     

High mobility nanocrystalline silicon transistors on clear plastic substrates

We demonstrate nanocrystalline silicon (nc-Si) top-gate thin-film transistors (TFTs) on optically clear, flexible plastic foil substrates. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150/spl deg/C. The n-channel nc-Si TFTs have saturation electron mobilities of 18 cm/sup 2/V/sup -1/s/sup -1/ and transconductances of 0.22 /spl mu/S/spl mu/m/sup -1/. With a channel width to length ratio of 2, these TFTs deliver up to 0.1 mA to bottom emitting electrophosphorescent organic light-emitting devices (OLEDs) which were fabricated on a separate glass substrate. These results suggest that high-current, small-area OLED driver TFTs can be made by a low-temperature process, compatible with flexible clear plastic substrates.