A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-/spl mu/m CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10/sup -13/.     

3.2-5 Gb/s, 100 km error-free soliton transmission with erbiumamplifiers and repeaters

For the transmissions, the transform-limited soliton pulse source is a gain-switched distributed-feedback laser diode with a narrowband spectral filter and erbium amplifiers. A LiNbO₃ light intensity modulator is used for pulse switching. The preemphasis technique for sending solitons over a long distance, in which an erbium optical repeater is installed every 25 km as a lumped amplifier, is used     

一种2.5 Gb/s LVDS接收器设计

基于SMIC 0.18 μm 1P6M 标准CMOS工艺,设计了一种2.5 Gb/s LVDS接收器电路。仿真结果表明,所设计的LVDS电路参数符合LVDS标准,LVDS接收器的输出信号上升沿抖动约为0.76 ps,有效版图面积约为(83×44) μm²,能应用于高速数据接口。     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

24万兆比特每秒激光器/光调制器驱动电路

一种应用于高速光纤通讯系统的激光二极管／调制器的单片集成驱动电路已开发成功。该电路的制造使用了0．2μm PHEMT工艺,它的工作信号带宽超过12GHz。在12Gb／s速率下测得了摆幅峰值为3．4V的输出信号眼图。基于实验结果,我们判断该电路的最大工作速率超过24Gb／s。该驱动器电路使用单电源-4．5V供电,功耗小于1．8W。     

一种新型6.25 Gb/s CTLE均衡器的设计

为了改善传统CTLE均衡器的均衡能力较低、使用大电容造成版图面积较大等缺点,设计了一款采用多级并联反馈网络的新型CTLE均衡器。该均衡器可用于高速串行通信,其频率补偿点以及补偿强度可调,能正确传输不同数据率的串行信号。基于SMIC 40 nm CMOS工艺对电路进行设计,仿真结果显示,在6.25 Gb/s的最大数据率下,最大补偿能力为13.8 dB,平均功耗为0.7 mW,版图尺寸为14.3 μm×13 μm。     

2.5Gb/s限幅放大器设计

文章采用TSMC 0．35μmSiGe工艺实现了数据率达到2．5Gh／s的光纤通道限幅放大器。限幅放大器信号通道利用多级放大方式，降低了输出信号上升／下降时间，减小了级间驱动能力不匹配对信号完整性的影响：通过负反馈环路消除了信号通道上的偏移电压，采用独特的迟滞技术，使检测电路的迟滞对外接电阻变化不敏感。仿真结果证明设计方法是有效的。     

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

A hybrid CDR is presented that embeds a 5 blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual jitter tolerances. In this implementation, the jitter tolerance of a phase-tracking CDR alone is increased by a factor of 32 at frequencies below its loop filter's bandwidth, while maintaining the high-frequency jitter tolerance of a 5x blind-oversampling CDR. Measured data from a 0.11 mum CMOS test chip at 2.4 Gb/s confirm a 200 UI peak-to-peak jitter tolerance for a 200 kHz jitter. The test chip operates from 1.9 Gb/s to 3.5 Gb/s with a BER less than 10^-11, consuming 115 mW at 2.4 Gb/s.     

一种4Gb/s低压差分信号比较器的低抖动优化设计

基于低压差分信号比较器的结构,研究了影响比较器输出抖动的各种因素,并指出:根据差分信号的输入摆幅来优化电路有助于降低电路的输出抖动.基于0.13 μm CMOS工艺,优化设计了一种低抖动的低压差分信号比较器电路.仿真结果显示,该低压差分信号比较器电路能够转换传输速率高达4 Gb/s的信号,在输入信号差分摆幅确定的条件下,其额外引入的峰峰值抖动为2 ps.     

千兆比特数据率LVDS接口电路设计

设计了一个采用0.18μm1.8V/3.3V CMOS工艺制造的千兆比特数据率LVDS I/O接口电路。发送器电路采用内部参考电流源和片上匹配电阻,使工艺偏差、温度变化对输出信号幅度的影响减小50%;接收器电路采用一种改进的结构,通过检测输入共模电平,自适应调整预放大器偏置电压,保证跨导Gm在LVDS标准[1]要求的共模范围内恒定,因此芯片在接收端引入的抖动最小。芯片面积0.175mm2,3.3V电源电压下功耗为33mW,测试表明此接口传输速率达到1Gb/s。     

2.5Gb/s CMOS光接收机限幅放大器

采用SMIC 0.18μm CMOS工艺设计了光接收机限幅放大器.该放大器采用全差分结构,利用退化电容技术增加高频时放大器的等效跨导,并在Cherry-Hooper结构里引入有源电感反馈代替传统的电阻反馈来扩展带宽.Hspice仿真结果表明限幅放大器具有46dB的中频增益、3.2GHz带宽,当输入电压信号从3.6mVPP到1.7VPP变化时,50Ω负载线上的输出电压限幅在340mVPP,输出眼图稳定清晰.核心电路功耗20.431mW.     

3.125Gb/s基于PS/PI型的时钟与数据恢复电路设计

基于标准0.18μmCMOS工艺,设计了一种全速率PS/PI型时钟与数据恢复(CDR)电路。该电路主要由bang-bang型鉴相器、数字控制模块、分接器、相位选择器以及相位插值器等模块构成。根据本CDR的特点,提出了一种在分接器后对超前、滞后信息进行统计比较得到一组低速信号来解决高速模拟电路和低速数字电路之间的接口问题。     

2.5 Gb/s Optical Transponder技术与设计

网络容量增长的同时也促进了光纤通信技术的发展，使得宽带传输和接入方式处于越来越重要的地位，如何有效地解决光纤干线上和大部分基于电缆局域网的信号转换成为亟待解决的问题，光收发器(opticaltransponder)很好地解决了宽带传输和接入的这一“瓶颈”问题．2．5Gb／s是目前最流行的传输速率，其相应transponder用于SDH／SonetOC-48／STM-16的光／电接口．文章介绍了2．5Gb／soptical transponder的功能、结构等技术和相应的设计方案．     

2.5 Gb/s Optical Transponder技术与设计

网络容量增长的同时也促进了光纤通信技术的发展,使得宽带传输和接入方式处于越来越重要的地位,如何有效地解决光纤干线上和大部分基于电缆局域网的信号转换成为亟待解决的问题,光收发器(opticaltransponder)很好地解决了宽带传输和接入的这一“瓶颈”问题。2.5 Gb/s是目前最流行的传输速率,其相应transponder用于SDH/Sonet OC-48/STM-16的光/电接口。文章介绍了2.5 Gb/s optical transponder的功能、结构等技术和相应的设计方案。     

一个1.12Gb/s 11.3mW LVDS发射器设计

这篇文章提出了基于0.18μm混合信号CMOS工艺,工作在1.8V电源电压下的1.12Gb/s 11.3mW的发射器。该发射器采用了LVDS技术实现了高速传输,输出共模为1.2V。MUX和LVDS驱动电路对于发射器实现高速数据传输而言是很重要的。这篇文章提出了一个高能效的单级14:1 MUX和一个可调LVDS驱动电路,该驱动电路能够驱动不同的负载而仅增加很少的功耗。该发射器的芯片面积为970μm×560μm,实现了低功耗和可调驱动能力。     

46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider insilicon bipolar technology

High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s     

All-Optical Packet-Switching Decoder Design and Demonstration at 10 Gb/s

A 3 times 8 all-optical decoder based on cross-polarization modulation in semiconductor optical amplifiers is demonstrated for the first time to our knowledge. The design requires a single active optical device per output. Experimental results are shown for return-to-zero modulated 10-Gb/s signals. Applications include label processing in optical packet switched optical networks     

基于系数可调FFE的10 Gb/s发送端的设计

采用SMIC 40 nm CMOS工艺,设计了一种工作在10 Gb/s的SerDes高速串行接口发送端电路,并创新性地提出了一种系数可调的FFE结构,使电路能适用于不同衰减的信道。电路主要模块为复接器、3阶FFE均衡器。复接器采用经典半速率结构,使用数字模块搭建,降低了功耗,并通过设计使采样时钟位于输入的最佳采样点,抑制了毛刺的产生。FFE均衡器采用结构简单的TSPC类型D触发器、低功耗的选择器和系数可调节抽头加法电路,使信号达到均衡效果,补偿信道的衰减。仿真结果显示,电路稳定工作于10 Gb/s,在1.1 V电源电压下功耗仅为30 mW。     

2.5 Gb/s PS/PI型半速率时钟数据恢复电路设计

采用标准0.18 μm CMOS工艺,设计了一种相位选择(PS)/相位插值(PI)型半速率时钟数据恢复电路。该电路主要由半速率Bang-Bang鉴相器、改进型PS/PI电路、数字滤波器和数字控制器等模块构成。改进型PS/PI电路通过两个相位选择器和两个相位插值器实现正交时钟的产生,相较于传统结构,减少了两个相位选择器,降低了复杂度和功耗。数字滤波器和数字控制器通过Verilog代码自动综合生成,降低了设计难度。Cadence仿真结果表明,输入2.5 Gb/s伪随机数据时,电路在1.8 μs时锁定,锁定后恢复出的时钟和数据峰峰值抖动分别为17.71 ps和17.89 ps,可以满足短距离I/O接口通信的需求。     

Bandwidth virtualization enables long-haul WDM transport of 40 Gb/s and 100 Gb/s services

This article describes how bandwidth virtualization can enable transmission of ultra-high bandwidth 40 Gb/s and 100 Gb/s services over existing optical transport networks independently of the underlying network infrastructure. An overview of the technology alternatives available to enable high-bandwidth service transport is provided, along with a discussion of the relative merits of different approaches. The authors describe how wavelength division multiplexing, using large- scale photonic integrated circuits combined with the use of a digital virtual concatenation mapping protocol, can be used to enable decoupling of 40 Gb/s and 100 Gb/s service provisioning from the underlying optical link engineering, thereby enabling bandwidth virtualization. Real-world implementation examples of bandwidth virtualization are provided, including 40 Gb/s service transmission over a 2000-km fiber link with 65 ps of peak PMD, a field trial of 40 Gb/s service transmission over an 8477-km trans-oceanic network, and finally a field trial of a pre-standard 100 gigabit Ethernet service transmission over a 4000-km terrestrial long-haul network.