Model of low frequency noise in polycrystalline silicon thin-filmtransistors

A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements     

Enhanced degradation in polycrystalline silicon thin-filmtransistors under dynamic hot-carrier stress

We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G_{m max}) in static stress, G_{m max} in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation     

Integrated amorphous and polycrystalline silicon thin-filmtransistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of ~15 cm²/Vs, the amorphous silicon transistors have a linear mobility of ~0.7 cm²/Vs and both have an ON/OFF current ratios of >10⁵. Rehydrogenation of amorphous silicon after the 600°C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper     

Flicker noise in silicon planar transistors

Flicker noise may be characterised by a single parameter ?F, which is the frequency at which flicker noise becomes equal to shot noise. Many devices show ?F to be as low as 60 Hz, and give a noise figure of <1dB at 25 Hz. This is not in accordance with a recently published formula.     

Negative gate bias instability in polycrystalline silicon TFT's

Degradation of the device characteristics of poly-Si TFT's are seen following negative gate bias stress at elevated temperatures. The degradation has two components, One component is the trapping of holes in the gate oxide; this is a similar phenomenon to the so called `negative bias instability' seen in mono-Si MOSFETs. The other component is state formation and removal in the poly-Si bulk, or at the poly-Si-SiO₂ interface, and this is similar to that seen in αSi:H TFT's. The states formed are not the same as those produced by hot carrier stressing     

Hot carrier effects in n-channel polycrystalline silicon thin-filmtransistors: a correlation between off-current and transconductancevariations

The application of bias-stresses with high source-drain voltage and different gate voltages in polycrystalline thin-film transistors modifies the transconductance as well as the off current. These effects have been explained in terms of hot-holes injection into the gate insulator causing the formation of trap centers in the oxide and interface states near the drain     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics     

Three-mask polycrystalline silicon TFT with metallic gate and junctions

Polycrystalline silicon thin-film transistors (TFTs) with metallic gates and junctions realized using a three-mask metal-replaced junction (MERJ) technology have been fabricated and characterized. Compared to those of a conventional TFT, the process of making a MERJ TFT is simplified, and the resistance of the junctions and gate is reduced. The low resistance of the metallic junctions allows a greater recovery of the intrinsic characteristics of a MERJ TFT, and the reduced signal delay on a low-resistance metallic gate line makes the TFT particularly suitable for realizing large-area active-matrix flat-panel displays.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Flicker noise in transistors

Measurements of the noise voltage appearing at the ac open-circuited emitter of a transistor with its collector ac grounded and with both an external base resistance and the operating point as parameters can be used to study the location of flicker-noise sources in transistors. A general flicker-noise model is assumed. It is shown by this method of measurement that for many modern transistors the flicker-noise sources are adequately represented by a single noise current generator connected in parallel with the emitter-base junction. The method permits evaluation of the magnitude of both the correlated and uncorrelated parts of a possible collector-base flicker-noise current generator as well as measurement of the emitter-base generator.     

Flicker noise analysis of laminar voltage signals of porous silicon films

A special kind of noise analysis is applied on voltage signals recorded when the electrochemical etching of crystalline surfaces of silicon is performed. The resulting material, named porous silicon (PS), exhibits nanocrystalline formations and has interesting properties which can be employed in the development of optical, electronic or biological sensor devices. These characteristics depend mostly on the resulting morphology after etching. The flicker noise analysis is a suitable way to extract information on the dynamics of the pore formation and its correlation with morphology. This study shows some of the analysis results.     

Planarized copper gate hydrogenated amorphous-silicon thin-filmtransistors for AM-LCDs

We report the first fabrication of inverted-staggered back-channel-etch hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a planarized Cu gate electrode. The Cu gate-planarized (GP) a-Si:H TFTs, incorporating benzocyclobutene and a-SiN_x:H as a double-layer gate insulator, had a field-effect mobility of 0.75 cm²/V-s, a threshold voltage of 4.92 V, and a subthreshold swing (S) of 0.48 V/dec. These results demonstrate that the GP-TFTs can have an electrical performance comparable with the conventional TFTs without gate planarization. Thus, the gate planarization technology is suitable for application in large-area and high-resolution active-matrix liquid-crystal displays     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

Flicker noise in Gunn diodes

The low frequency noise of Gunn diodes fabricated by either a planar technique or a mesa technique on a GaAs substrate was measured. The existence of 1/? noise was demonstrated. We were unable to discriminate between the number fluctuation model and the mobility fluctuation model of 1/? noise. It seems from the data that Hooge's parameter α, if present, is not field dependent as in Si. Independent α(E) measurements might allow us to discriminate between the two models.     

Self-passivated copper gates for amorphous silicon thin-filmtransistors

A solution to the amorphous silicon transistor gate metallization problem in active matrix liquid crystal displays (AMLCD's) is demonstrated, in the form of a self-passivated copper (Cu) process. Cu is passivated by a self-aligned chromium (Cr) oxide encapsulation formed by surface segregation of Cr in dilute Cu-10-30 at.%Cr alloys at 400°C, solving the problems of chemical reactivity during the plasma deposition, diffusion, poor adhesion to the substrate, and oxidation. The performance of self-passivated Cu bottom-gate thin-film transistors (TFT's) and their stability during thermal bias stress testing is comparable to that of Cr-gate reference TFT's. The gate line resistivity (including encapsulation) is 4.5 μΩ·cm at present     

Flicker noise in Gunn diodes

Gunn diodes exhibit current noise which is almost independent of whether the diode is oscillating. The current noise has a flicker characteristic, and fluctuations in the current are correlated with fluctuations in the frequency of the oscillator.     

The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon

An abnormal gate oxide failure was found in DRAM using deep submicron technology. Contrary to the general dielectric extrinsic breakdown, the degradation of gate oxide integrity was shown only in the gate lines of a small dimension, not in those of a large dimension. This abnormal oxide breakdown is due to the voids in the polycrystalline silicon, which are at the center of gate line with a small dimension. These voids are formed by both chemical potential difference and stress enhanced diffusion of polycrystalline silicon. The suppression method of these voids using sufficient source of polycrystalline silicon is proposed.     

Flicker phase noise in transistorized amplifier

In this article, the relation between the frequency stability due to the flicker phase noise (phase-power spectrum densityS _Δϕ1'(f) in frequency domain and Allen variance γ _y ² {τ} in time domain) and the parameters of the transistors has been derived and experimentally verified.     

Flicker noise in MOSFETs with gate-voltage-dependent mobility

Flicker noise measurements in MOSFETs at low drain bias are explained in terms of the dependence of the carrier mobility on the gate voltage of the form μ₀₀[1 + β(V_G ? V_T ? V₀)]^?1. Excellent agreement, both for the (I_d, V_g) characteristic and for the flicker noise, is obtained. The noise current spectrum is expressed in the normalized functions f(y₀, y₁) and f(y₀, y₁)/y₀ in terms of the bias parameters y₀ = β(V_g ? V_T) and y₁ = β(V_g ? V_T ? V_d).