共查询到20条相似文献,搜索用时 15 毫秒
1.
For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. 相似文献
2.
本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型.并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究.该模型中考虑以下参数:金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分.结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL.同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率.此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高.数值模拟器ISE验证了该模型的正确性. 相似文献
3.
4.
On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs. 相似文献
5.
6.
Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE. 相似文献
7.
A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs 总被引:2,自引:0,他引:2
For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator. 相似文献
8.
We present a temperature dependent model for the threshold voltage Vt and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition Vt is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both Vt and S, and also the rate of change of Vt with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures. 相似文献
9.
10.
11.
A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration. 相似文献
12.
A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks
n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations. 相似文献
13.
研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。 相似文献
14.
PolySOI MOSFETs have been fabricated on undoped and doped polycrystalline silicon films and characterized to study the effect of doping on grain boundary passivation. The grain boundary trap density (NST) and threshold voltages have been extracted experimentally to evaluate the extent of grain boundary passivation by the dopants. Charge sheet model based on the effective doping concentration has been employed to analytically estimate the threshold voltages using the experimentally determined grain boundary trap density and grain size (Lg) as model parameters. The variation of threshold voltages with increasing doping concentration for the range of NA ? (NST/Lg) has been studied both by simulation and experiments and the results are presented. Analytically estimated threshold voltages and experimental results show that the threshold voltage falls with increase in the dopant concentration and that this effect is indeed due to the reduction in NST as a result of the grain boundary passivation by the dopants. 相似文献
15.
Rajesh Saha Brinda Bhowmick Srimanta Baishya 《International Journal of Electronics》2019,106(4):553-566
An analytical modelling of the subthreshold surface potential, threshold voltage (VT) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and VT models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate. 相似文献
16.
基于流体动力学能量输运模型 ,利用二维仿真软件 Medici对深亚微米槽栅 PMOS器件的结构参数 ,如凹槽拐角、负结深、沟道和衬底掺杂浓度对器件抗热载流子特性和短沟道效应抑制作用的影响进行了研究 .并从器件内部物理机理上对研究结果进行了解释 .研究发现 ,随着凹槽拐角、负结深的增大和沟道杂质浓度的提高 ,器件的抗热载流子能力增强 ,阈值电压升高 ,对短沟道效应的抑制作用增强 .而随着衬底掺杂浓度的提高 ,虽然器件的短沟道抑制能力增强 ,但抗热载流子性能降低 相似文献
17.
Darsen D. Lu Mohan V. DungaChung-Hsun Lin Ali M. NiknejadChenming Hu 《Solid-state electronics》2011,62(1):31-39
In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I-V and C-V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors. 相似文献
18.
Yuusuke Tanaka Akira Tanabe Katsumi Suzuki Tsutomu Miyatake Masaki Hirose 《Journal of Electronic Materials》1998,27(8):936-940
The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel
metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs,
device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while
the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to
be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through
the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states
are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation
in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm2. 相似文献
19.
C. S. Ho J. J. Liou H. L. Lo Y. H. Chang C. Chang K. Yu 《International Journal of Electronics》2013,100(3):137-148
In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance (R S/R D). Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the R S and R D can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the R S/R D increases with decreasing channel length and oxide thickness. 相似文献