Digital control of three-phase PWM inverter with LC filter

A digital control algorithm for the three-phase sinusoidal voltage inverter with an output LC filter has been developed. To take the transient of the LC filter during the discretization time into consideration, a fourth-order matrix state equation of the current and the voltage on the d-q frame is discretized. Precise discrete equations for the inverter are introduced. Using these equations, a deadbeat controller consisting of a d-g current minor loop and a d-q voltage major loop, with precise decoupling of the d-q components, was developed. The voltage major loop controller assures the sinusoidal output voltage and stabilizes the system. A deadbeat controller is used because both the current minor loop and the voltage major loop can used one sampling response. The validity of these techniques is confirmed by simulation studies. This method is expected to be useful for direct digital control of large-capacity sinusoidal voltage inverters using low-switching-frequency devices     

Designer's Casebook-compact detector stabilized LCoscillators

An averaging or peak-voltage detector is generally incorporated in an RC oscillator for stabilizing its amplitude. Corresponding circuitry for an LC oscillator, however, is usually cumbersome because it requires two LC circuits tuned to the same frequency. An amplifying circuit that operates as a linear current divider for LC oscillators to overcome this problem is presented     

A generic soft switching converter topology with a parallelnonlinear network for high-power application

A soft switching concept that derives from the resonant link and resonant pole power converters and combines the best features of resonant and hard switching converters is applied to a phase arm. The inductor of the resonant LC is designed to saturate, thus having effectively two inductance values: a very large value during the conduction period and a small value that is only active during switching. The advantage of this technique is that a resonant tank with smaller continuous ratings can be used without giving up the component count advantage of resonant power converters. Another feature, contrary to other resonant topologies, is that semiconductor switches need not be overdimensional for voltage and current rating     

The inductance matrix of a multiconductor transmission line inmultiple magnetic media

A simple relationship between the inductance matrix and the auxiliary capacitance matrix is given. For a multiconductor transmission line consisting of N_c conducting cylinders in inhomogeneous media consisting of N_d homogeneous regions with permeabilities μ_i and permittivities ϵ _i, the inductance matrix [L] for the line is obtained by solving the magnetostatic problem of N_c conductors in N_d regions with permeabilities μ _i. The capacitance matrix [C] for the line is obtained by solving the electrostatic problem of N_c conductors in N_d regions with permittivities ϵ _i. It is shown that [L]=μ₀ϵ₀[C^'] ^-1, where [C^'] is the capacitance matrix of an auxiliary electrostatic problem of N_c conductors in N_d regions with relative permittivities set equal to the reciprocals of the relative permeabilities of the magnetostatic problem, i.e. ϵ^' _i/ϵ₀=μ₀/μ_i     

Performance analysis of the Josephson DC flip-flop

A linear analytical model of the Josephson DC flip-flop is proposed. The model describes both the Baechtold's and Hebard's flip-flops. The output signal line is treated as either a single inductance or a transmission line with a finite impedance. The former leads to the lumped model, while the latter leads to the distributed model. The lumped model gives the load condition for successful reset. This is given as a relationship between the CR and L/ R time constant, where C is the device capacitance, L is the load inductance, and R is the load resistance. The switching delay is also described as a linear function of the CR and L/R. With the distributed circuit model, the load condition for successful reset is Z₀⩾R. Minimum delay is obtained at Z₀=R. Grounding one end of the output signal line reduces the delay more than the nongrounded configuration. The scalar relationship of the switching delay and the power consumption to the design rule is discussed     

Closed-form expressions for interconnection delay, coupling, andcrosstalk in VLSIs

A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed     

A low-loss bandpass filter using electrically coupled high-Q TM01δ dielectric rod resonators

For a TM_01δ mode dielectric rod resonator placed coaxially in a TM₀₁ cutoff circular waveguide, characteristics such as the resonant frequency, its temperature coefficient, the unloaded Q, and the other resonances are discussed on the bases of accurate calculations using the mode-matching method. The results show that this resonator compares favorably with a conventional TE_01δ mode dielectric resonator, particularly for realization of a high unloaded Q. Analytical results also verify that interresonator coupling between these two resonators can be expressed equivalently by a capacitively coupled LC resonant circuit. A four-stage Chebyshev filter having a ripple of 0.035 dB and an equiripple bandwidth of 27 MHz at a center frequency of 11.958 GHz was fabricated using these resonators. Its insertion loss is 0.5 dB, which corresponds to an unloaded Q of 17000, and no spurious response appears in the frequency range below 17 GHz     

Automatic VT extractors based on ann×n2 MOS transistor array and theirapplication

The development of incremental and decremental V_T extractors based on the square-law characteristic and an n ×n² transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V_T extraction, parameter K of an MOS transistor can also be extracted automatically using the V_T extractor, without any need of calculation and delay, and the extracted V_T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V_T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V_T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented     

Harmonic current reduction in a three-phase diode bridge rectifier

A novel method for reducing harmonic currents on the AC supply side of a three-phase bridge rectifier is presented. The principle of the method is to modify the current waveforms in the DC windings of the converter transformer by injecting a third harmonic current into the neutral point of the transformer. Passive LC filters connected between the rectifier output and the secondary neutral point act as third harmonic current sources. The effectiveness of the method is confirmed by laboratory recordings     

Modeling and experimental results for C(V) in anabrupt isotype n Al0.5Ga0.5As/GaAs heterojunction

The differential capacitance C of an abrupt isotype n Al_0.5 Ga_0.5As/GaAs heterojunction has been modeled by directly calculating the dependence of the space charge on the voltage V at its terminals. The electron charge distribution was calculated considering the 2-D electron gas by simultaneously solving the Schrodinger and the Poisson equations, DX centers included. Results from this model predict an asymmetric bell-shape dependence of C on V, with a maximum near the contact potential, and are in good agreement with experiment. This further provides experimental evidence of Γ-Γ and X-X valley coupling for electrons traveling across the heterojunction. For voltage values not too close to the contact potential, it was possible to find a simple method, based on a total depletion, that gives a good fit to experiment     

Channel-length measurement technique based on a floating-gatedevice

By measuring the threshold voltage of the structure for several drawn channel lengths, ΔL is extracted. This technique is the translation of a capacitance measurement into a threshold measurement and as such is accurate and simple to perform. Since the technique does not involve a current flow through the transistor under test, it is especially advantageous for L_eff measurements on lightly-doped drain (LDD) and double-diffused drain (DDD) short-channel devices     

Design of a thyristor snubber circuit by considering the reverserecovery process

Design procedures are presented for the snubber circuit in power electronic circuits by considering the reverse recovery process of the thyristor. The thyristor turnoff model, whose parameters are determined for best fitting to the device characteristics given on the data sheets, is applied to analyze the behavior of the snubber circuit with and without a saturable reactor during the reverse recovery time of the power device. Based on the turnoff model, exact expressions are derived for various quantities of interest including the maximum device stress, maximum reverse dv/dt, the reverse energy loss of a power device, and the total turnoff loss in the device plus the associated snubber circuit. Utilizing the analysis results, a systematic approach to the snubber-circuit design with the stray inductance taken into account is described. It is concluded that the proposed approach is very useful in the simulation of turnoff characteristics of the power device, snubber-circuit designs, and loss calculations in power circuits     

Overshoot-controlled RLC interconnections

How overshoot in the step response of a circuit involving an RLC line can be controlled using a combination of driver and line resistance that depends on the load capacitance is shown. The no-peak condition or its equivalent is used to relate line parameters to the driver and load impedances. This no-peak condition generalizes the impedance matching customarily used for lossless lines, i.e. it provides an alternative to the traditional choice R_D=√ L/C. The results allow improved circuit response without risk of overshoot, for example, by reduction of driver resistance below √L/C for cases where line resistance is unavoidable and/or where load capacitance is not negligible compared to line capacitance. The algebraic formulas derived are more effective than case-by-case numerical simulations for analyzing scaling and technology issues, whether on-chip, or at the packaging, board, or system levels     

Zero-voltage-switched quasi-resonant buck and flybackconverters-experimental results at 10 MHz

Experimental results are presented for buck and flyback zero-voltage-switched (ZVS) quasi-resonant converters (QRCs) operating above 5 MHz. A design procedure for a buck ZVS QRC is proposed that minimizes voltage stress to the power MOSFET transistor while maintaining zero voltage switching for specified ranges of input voltage and load resistance. A quasi-resonant gate drive scheme is also proposed and implemented in a buck converter. The drive is simple and provides high switching speed. Power dissipation in the gate drive is substantially reduced due to the quasi-resonant operation. The ZVS QRC technique described is suitable for very-high-frequency operation due to its ability to reduce dynamic turn-on losses, Miller effect, dv/dt, and di//dt and can be applied in distributed onboard power supplies     

Thermal parameter estimation using recursive identification

A novel method that converts a semiconductor transient thermal impedance curve (TTIC) into an equivalent thermal RC network model is presented. Thermal resistance (R) and thermal capacitance (C) parameters of the model are identified using manufacturer's data and offline recursive least square techniques. Relevant estimation theory concepts and the formulation of an appropriate model for the identification process are given. Model synthesis is illustrated using an isolated base power transistor module. The application of time decoupled theory for high order thermal models is outlined. Simulation of junction temperature responses using model and manufacturer TTICs are compared. Estimated parameter validity is further confirmed by parameter calculation obtained from module physical dimensions     

The importance of losses in the coupling of transmission lines

A simple model for weakly coupled lossy transmission lines of finite length has recently been proposed by Olsen (1984). He derived a simple formula for the coupling voltage on a load situated at one extremity of the undriven wire. The importance of the coupling due to losses on this voltage with respect to the coupling due to capacitance and inductance is investigated in this paper. It is found that only in a special case, called the resonance matching case, is the role of the losses dominant in the coupling process. This case is characterized by the condition that the characteristic impedance of the wires squared by equal to the product of two loads Z_LG and Z _0R situated at opposite ends of the driven and the undriven wire     

Vector S-parameter measurements of the superconductingvortex flow transistor

Vector S-parameter measurements of the superconducting vortex flow transistor (VFT) are presented. The measurements were obtained for frequencies up to 100 MHz on VFTs that had a calculated transmit-time cutoff frequency of 5 GHz. An equivalent circuit model that includes calculations of the VFT transresistance, input inductance, and feedthrough capacitance is derived from these measurements. The measurements are limited to an upper frequency of 100 MHz due to crosstalk in the low-impedance system     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

Si IC-compatible inductors and LC passive filters

Passive inductors and LC filters fabricated in standard Si IC technology are demonstrated. Q-factors from three to eight and inductors up to 10 nH in the gigahertz range have been realized. Measurements on a five-pole maximally flat low-pass filter give midband insertion loss and -3 dB bandwidth close to the nominal design values of 2.25 dB and 880 MHz     

Transistor design for predictable power gain at maximum frequency

Equations which define the neutral base width, collector doping, and epitaxial collector thickness of a bipolar transistor giving a specified unilateral power gain at the highest frequency, possible are derived. Emitter-base capacitance, emitter delay, emitter stripe width, base doping, and the operating base-collector voltage are assumed to be known and fixed. The hybrid-π equivalent circuit is assumed valid up to the transition frequency f_t. Peak f_max (maximum oscillation frequency) is examined as a function of the collector doping. Maximizing f_max at all costs leads to a design with an f_t which approaches zero. In designing a transistor, the two figures of merit must be traded off against each other. A simple expression giving maximum f_max/f_t is derived and used to define the transistor design which gives some specified power gain at the highest possible frequency